Skip to content
Free planNo credit card requiredStart writing
AI for Research home
AI for Research home
Dashboard
Sign inGet started

Search 250 million research papers

Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.

About 2,287 papers for “Static random-access memory”

Static Random Access Memory Failure Analysis

Zhigang Song · Proceedings - International Symposium for Testing and Failure Analysis · 2025

Abstract Presentation slides for the ISTFA 2025 Tutorial session “Static Random Access Memory Failure Analysis.”

Cited by 0

Scalable Static Random Access Memory design

Wuu, John J. (John Jung-Sheun) · DSpace@MIT (Massachusetts Institute of Technology) · 1997

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.

Cited by 0Open access

Index Terms—Static Random-Access Memory (SRAM),

2016

Abstract—This paper presents the characterization and design of a Static Random Access Memory (SRAM) cell at nano scale ranges. The proposed SRAM cell incorporates a Single-Electron (SE) turnstile and a Single-Electron Transistor (SET)/MOS circuit in its operation, hence the hybrid nature. Differently from previous cells, the hybrid circuit is utilized to sense (measure) on a voltage-basis the presence of at least an electron as stored in memory, while the turnstile enables the single electron transfer in and out of the storage node. The two memory operations (read and write) are facilitated by utilizing these hybrid circuits; moreover the proposed SRAM cell shows compatibility with MOSFET technology. HSPICE simulation shows that the proposed SRAM cell operates correctly at 45 and 32 nm with good performance in terms of propagation delay, signal integrity, area, stability and power consumption. The extension of the above hybrid design to a Ternary Content Addressable Memory (TCAM) cell is also presented.

Cited by 0

Nano-optomechanical static random access memory (SRAM)

Bin Dong, Hong Cai, Yimin Gu et al. · 2015

This paper reports an on chip nano-optomechanical SRAM, which is integrated with light modulation system on a single silicon chip. In particular, a doubly-clamped silicon beam shows bistability due to the non-linear optical gradient force generated from a ring resonator. The memory states are assigned with two stable deformation positions, which can be switched by modulating the control light's power with the integrated optical modulator. The optical SRAM has write/read time around 120 ns, which is much faster as compared with traditional MEMS memory. Meanwhile, the write and read processes can happen concurrently without interference, which further reduces the time as compared with conventional electrical enabled SRAM.

Cited by 6

2D Materials‐Based Static Random‐Access Memory

Chang‐Ju Liu, Yi Wan, Lain‐Jong Li et al. · Advanced Materials · 2021

Abstract 2D transition‐metal dichalcogenide semiconductors, such as MoS 2 and WSe 2 , with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)‐based field‐effect transistor (FET) and static random‐access memory (SRAM) cells analyzing the impact of layer thickness reveals that the monolayer 2DM FET with superior electrostatics is beneficial for its ability to mitigate the read–write conflict in an SRAM cell at scaled technology nodes (1–2.1 nm). Moreover, the monolayer 2DM SRAM exhibits lower cell read access time and write time than the bilayer and trilayer 2DM SRAM cells at fixed leakage power. This simulation predicts that the optimization of 2DM SRAM designed with state‐of‐the‐art contact resistance, mobility, and equivalent oxide thickness leads to excellent stability and operation speed at the 1‐nm node. Applying the nanosheet (NS) gate‐all‐around (GAA) structure to 2DM further reduces cell read access time and write time and improves the area density of the SRAM cells, demonstrating a feasible scaling path beyond Si technology using 2DM NSFETs. In addition to the device design, the process challenges for 2DM NSFETs, including the cost‐effective stacking of 2DM layers, formation of electrical contacts, suspended 2DM channels, and GAA structures, are also discussed.

Cited by 30

www.ijstr.org Radiations On Static Random Access Memory Cell

Birinderjit Singh Kalyan · 2015

Abstract: With increased memory capacity usually comes increased bit line parasitice capacitance. This increased bit line capacitance in turn slows down voltage sensing and makes bit line voltage swing energy expensive resulting in slower more energy hungry memories. A full description of the various methods is beyond the scope of this article; instead, the focus is on providing primary developments that have taken place in the area of radiation effects on SRAM In this paper a comparision of different current mode sense amplifiers with flip flop structures using 0.35µm technology is presented with the effect of Radation effectv of 100 Krad exposures. Simulations results are given regarding sensing delay and power dissipation.

Cited by 0

4H-SiC Radiation Hardened Static Random Access Memory

Shin-Ichiro Kuroki, Toya Kai, Taisei Ozaki et al. · IEEE Electron Device Letters · 2024

4H-SiC static random-access memory (SRAM) was suggested and demonstrated for extreme-environment applications. The 4H-SiC SRAMs show the proper memory states with high static noise margins (SNMs). After exposure to a significant gamma-ray radiation of 810 kGy, the SRAMs continued to function effectively, maintaining positive SNM values necessary for proper memory operation. After the gamma-ray radiation, the SRAM operation was tested at high temperature, and it continued to function normally even at temperatures as high as 500°C.

Cited by 1

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory

Jiaona Zhang, Wanting Wang, Jiahao Zhu et al. · ACS Nano · 2024

Flexible static random access memory (SRAM) plays an important role in flexible electronics and systems. However, achieving SRAM with a small footprint, high flexibility, and high thermal stability has always been a big challenge. In this work, an ultraflexible six-transistor SRAM with high integration density is realized based on a monolithic three-dimensional (M3D) design. In this design, vertical stacked n-type indium gallium zinc oxide thin film transistors and p-type carbon nanotube transistors share common gate and drain electrodes, respectively, saving interlayer vias used in traditional M3D designs. This compact architecture reduces the footprint of the SRAM cell from a six-transistor to a four-transistor area, saving 33% of the area, and significantly enables the SRAM to have the highest flexibility among the reported ones, withstanding a harsh deforming process (6000 cycles of bending at a radius of 500 μm) without performance degradation. Moreover, this design facilitates the thermal stability of the SRAM under high temperature (333 K). It also exhibits great static and dynamic performance, with the highest normalized hold noise margin of 73.6%, a maximum gain of 151.2, and a minimum static power consumption of 3.15 μW in hold operation among the reported flexible SRAMs. This demonstration provides possibilities for SRAMs to be used in advanced wearable system applications.

Cited by 10

Ultra-low leakage static random access memory design

Didigam Anitha, Mohd. Masood Ahmad · Bulletin of Miscellaneous Information (Royal Gardens Kew) · 2023

An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropriate for hold mode applications. The simulations are carried out by using Cadence (Virtuoso Schematic and layout editor) tools with GPDK45-nm technology.

Cited by 0Open access

Power Aware 10T Static Random-Access Memory Design

Mooni Rahul, Velidandla Vaishnavi, Kasthuri Vyshnavi et al. · 2023

Our proposed 10T (PROP10T) SRAM cell is presented in this article. The important design metrics are assessed using HSPICE Monte Carlo Simulations. In our proposed 10T SRAM cell. The estimated results of PROP10T Static RAM cell are contrasted with the conventional 6T (CONV6T) and conventional 8T (CONV8T) Static RAM cell. Compared to the CONV6T and CONV8T, the PROP10T has demonstrated shorter read delay (TRA). The write delay (TWA) of PROP10T is now almost 4 times faster than CONV6and T's 1.2 times faster than CONV8 T's. On CONV6T and CONV8T, respectively, the proposed design improves RSNM (read static noise margin) by 3.1 and 2 dB [1].

Cited by 0

Nanoscale CMOS static random access memory (SRAM) design

Sunanda Ambulkar, Jitendra Kumar Mishra · 2023

The enormous demand for electronic devices has sparked a new revolution in VLSI technology. VLSI technology applications have extensively expanded to various electronic devices from mobile phones to military and defense operations, global communication systems, GPS positioning systems, satellites, radars, and the medical field – and the limit is yet to be reached. Almost all electronic gadgets contain memory as their integral part to store as well to perform various operations on the data wherever it is required. With the emergence of the Internet of Things (IoT) and Systems on Chips (SoCs), the demand for efficient design of SRAM cells is increasing very rapidly. In order to cope with the ever-increasing demand, the analysis of the various aspects of the SRAM cell design is a must. This chapter gives a brief introduction to the various SRAM cell including standard 6T SRAM as well as some advanced SRAM cells. Various performance parameters, and the impact of the nanoscale device on these parameters, are illustrated. A brief description of the various analyses using EDA tools is also provided. Furthermore, an 10T SRAM cell is discussed as an alternative for the IoT application.

Cited by 2

Ultra-low leakage static random access memory design

D. Anitha, Mohd. Masood Ahmad · International Journal of Reconfigurable and Embedded Systems (IJRES) · 2023

An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropriate for hold mode applications. The simulations are carried out by using Cadence (Virtuoso Schematic and layout editor) tools with GPDK45-nm technology.

Cited by 2Open access

Parallel programmable nonvolatile memory using ordinary static random access memory cells

T. Mizutani, Kiyoshi Takeuchi, Takuya Saraya et al. · Japanese Journal of Applied Physics · 2017

A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array. Successful 2 kbit NV writing is demonstrated using a device-matrix-array (DMA) test element group (TEG) fabricated by 0.18 µm technology.

Cited by 1

Designing of Graphene Nanoribbon based Static Random Access Memory

Abhishek Gune, Anu Gupta · 2013

In the post silicon era as the silicon reaches its fundamental scaling limits graphene nanoribbons is expected to take over and thus continue the Moore's law about the diminishing size of transistors. Graphene nanoribbons facilitates high speed low power switching applications. Low and high field mobilities of the graphene nanoribbons are found to be higher than the CNTs and CMOS keeping the same unit cell. Such properties of graphene nanoribbons are used in the paper to define RAM memory using GNRs as an effective substitute to CMOS and CNTFETs cache memory. Graphene nanoribbon crossbars are used as the basic programmable devices. This 2-D arrangement of GNRs creates programmable diodes at intersection of each horizontal and vertical GNR rod thus opening up new avenues for building high speed memory and digital devices. The graphene nanoribbons based memory is better than the SRAM in terms of speed, density and performance metrics as well. GNR based memory would be operating in the 10 nanometres scale and would be 25-50 per cent denser than the existing SRAM. The GNR based volatile memory would be ternary in nature and thus would account for 3^x bits of memory for x number of programmable node in the graphene nanoribbon architecture. By using the cross bar technique even denser GNR based memory could be produced.

Cited by 0

Deep submicron radiation hardened static random-access memory IP

Kostrov, A. I. · Репозиторий БГУИР (BSUIR Repository) · 2013

Modern System-on-a-Chip (SoC) is impossible to develop without built-in memory blocks. The availability of embedded memory enables SoC to perform fast, complex operations with large data arrays. Therefore the percentage of chip area occupied by various memories is constantly growing. Design of ICs which include large-scale memory blocks requires special software – IP Memory Block Compiler that would permit netlist and die topology to be created. Memory compilers allow quickly and automatically generate specifically sized memory blocks to be used in the design of ASICs.

Cited by 0

On design of multiple-valued static random-access-memory

Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto · 2002

General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are proposed and simulated with PSPICE. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5- mu m CMOS technology. Both PSPICE simulations and experiments indicate that the general theories presented are very useful and effective tools in optimal design and circuit realization of multiple-valued static RAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 5