J. A. García · Optical Engineering · 2007
Under oscillatory behavior of the net profit of transmission over time, heavy losses may be incurred in the form of foregone opportunities in the future if the transmission system prefers to transmit low-cost bit resources at this time over conserving for the future. This oscillatory behavior over time necessitates devising a stabilizing scheme for its optimal use in the transmission. Here we examine an optimal bit-saving path over time. During an initial period, the transmission system prioritizes exhaustible bit reserves of low transmission cost at the maximum available capacity and allocates gross transmission income partly to transmission and the rest is saved and invested to increase the degree of knowledge; and in the second period, once these low-cost bit reserves are exhausted, it is necessary to switch to a source of transmission solely from returns on current degree of knowledge, which initially includes highly insignificant bit streams. For knowledge-poor transmission systems the optimal bit-saving path differs sharply from that for region-based approaches with higher share of knowledge in the transmission's initial wealth. Also, the bit-saving path is highly dependent on the low-cost bitstreams life. We give a comparison in performance of the state of the art codec in progressive transmission against an algorithm which implements the saving path. It appears that the bit saving may be used with acceptable image fidelity.
Cited by 2
Arockia David Roy Kulandai, Thomas Schwarz · Híradástechnika/Infocommunications journal · 2022
New generations of non-volatile random access memories will combine the best features of memory (access times, byte addressability) with the best features of storage (non-volatility, low costs per byte). Some, like PCM, have a limited endurance. All will only consume energy when accessed, but writes will use much more energy than reads. These characteristics put a cost on flipping bits in memory. Bit-flip aware data structures lower the number of bits flipped by not resetting fields to zero to indicate a deleted record but by using bit-maps. If given a choice of where to over-write data, they will select the location which results in a lower number of bit-flips. We calculate the expected bit-flip savings of this strategy and derive a rule to determine the number of the possible candidate locations.
Cited by 0Open access
Král, Vojtěch · Brno University of Technology Digital Library (Brno University of Technology) · 2022
Diplomová práce se zabývá typy výkonových ztrát v technologii CMOS a následně jejich řešením metodami nízké spotřeby, které lze použít v oblasti zákaznických integrovaných obvodů. Jednou z možných metod pro nízkou spotřebu výkonu je vícebitový pulzní klopný obvod, který lze použít jako náhradu za standardní vícebitový klopný obvod typu master-slave. Vícebitový pulzní klopný obvod se skládá ze dvou částí, pulzního generátoru a pulzního klopného obvodu. V diplomové práci jsou popsané topologie, které mohou být použité. Konečná topologie byla vybraná na základě nízké spotřeby a plochy. Z vybrané topologie je vytvořeno schéma vícebitového pulzního klopného obvodu, které je porovnáno se schématem vícebitového klopného obvodu. Následně jsou vytvořeny layouty potřebných vícebitových pulzních klopných obvodů a porovnány jsou se standardními layouty vícebitových klopných obvodů. V závěru práce jsou navrhnuté vícebitové pulzní klopné obvody odsimulovány v jednoduchém designu.
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J. A. García, Rosa Rodríguez‐Sánchez, J. Fdez‐Valdivia · Journal of Visual Communication and Image Representation · 2010
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Nianxiong Tan, Sandra Eriksson, Lars Wanhammar · 2002
The bit-serial processing technique arises to be a competitor of the traditional bit-parallel processing technique to implement DSP ASICs, because the bit-serial implementation of DSP ASICs usually results in small communication cost and compact processing elements. However, shift registers are usually used to realize delays required by the DSP algorithms. Long shift registers consume a lot of power for they are clocked at very high frequency. More troublesome is that the power associated with driving a lot of clocked transistors has to be supplied by the clock lines (not power supply lines), which may cause clock distribution problem. In this paper, we propose a power-saving technique without speed penalty by getting rid of unnecessary data shifting and long shift registers. All the delay elements in the traditional long shift registers are realized by DRAM-alike memory cells and data is not shifted but accessed by using shared cyclical address decoders. The measurement of a test chip indicates a power saving by 4 times when we need to use 15 16-bit shift registers. More power saving is expected when we need more shift registers for large DSP ASICs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 7
Mark Po-Hung Lin, Chih‐Cheng Hsu, Yao-Tsung Chang · 2011
In modern large-scale, high-speed digital integrated circuit (IC) design, power consumption of the clock network usually dominates the dynamic power of the chip due to its highest switching rate. To effectively minimize the power consumption of the clock network, recent studies have been investigating the usage of multi-bit flip-flops (MBFFs). This paper presents the advantages of applying MBFFs, introduces various MBFF design flows, surveys key techniques for design optimization with MBFFs, and provides some future research directions in clock power saving with MBFFs.
Cited by 29
J.W. Snively · Proceedings of the IEEE · 1965
Cited by 1
Vincenzo Eramo, M. Listanti, Francesco G. Lavacca et al. · 2017
Cloud Radio Access Network (C-RAN) or centralized RAN could be seen as a promising solution to deal the 5G requirements. Traditional C-RANs are organized as a three-element network, that contains Base Band Unit (BBU) pool, Radio Radio Remote Unit (RRU) and the network interconnecting BBUs and RRUs called fronthaul. The BBU provides baseband signal processing functions and the RRU provides Radio Frequency signal transmission and reception functions. In this paper we propose procedures for the dimensioning of the transport network resources in the following scenario: i) all of the physical layer functions are implemented in the BBU and the signal samples are transported on Common Public Radio Interface (CPRI) flows; ii) Ethernet traffic is also transported for the use of traditional Radio Base Stations (RBS); iii) bandwidth saving techniques are applied by means of a reconfiguration of CPRI line bit rate so as to reduce the number of circuits of the transport network in the low traffic scenario. We show how the application of the introduced techniques allows for a saving of bandwidth in the order of 80%.
Cited by 2
Kim Bone, Ben Bradley, İbrahim Kale · Offshore Technology Conference · 2019
Abstract An offshore field has presented a challenging intermediate drilling application. The 2200-m section was drilled in a 17.5-in. hole to 3700-m true vertical depth. The lithogy of the section is variable, beginning with a soft claystone, followed by several sandstone formations, an 1100-m interbedded sandstone and claystone interval, a 125-m hard carbonate, and 50m of softer claystone before the casing point. The challenges presented in recent offset wells included high stick/slip, high levels of drill bit cutting structure wear and drill bit body erosion. Polycrystalline diamond compact (PDC) bit designs utilized in recent offsets varied from six to nine blades, with the interval requiring two or three bits to complete the interval. Based on results from other challenging offshore applications, including improved durability and drilling dynamics, the next-generation PDC and roller-cone hybrid drill bit (hybrid) with improved design features was selected for the application. Improved design features included a new increased blade count concept, combined with a sharp and dense roller-cone cutting structure. The application of the next-generation hybrid drill bit design delivered a reduction in drilling time and an improvement to drilling dynamics compared to offset wells drilled with conventional technology. Compared to the best offset well drilled in 17.5-in. hole a reduction in total drilling time of 59.4hrs (31%) was achieved. The reduction in drilling time resulted from both an increase in on bottom ROP of 32% and the removal a bit trip (19 hours) due to the interval being drilled in one run for the first time. Associated with the reduced drilling time, improvements in drilling dynamics were observed with stick/slip reduced by 73%. This paper illustrates the study of the application, applied learnings from new technology developments in hybrid technology evolution, and the subsequent improvements in drilling dynamics that resulted in improved penetration rates and cost savings in this challenging application.
Cited by 6
Xiaolong Huang, I. Rubin · Wireless Networks · 2008
Cited by 4
T. Satoh, T. Nagashima, K. Itoh et al. · 2013
We experimentally investigate the realization of low power consumption optical quantization with 7-bit resolution. We confirm the resolution improvement without increment of the signal power by incorporating the spectral compression technique using a phase modulator.
Cited by 10
Fumikazu Inuzuka, Toshifumi Nakamura, Hidemi Noguchi et al. · 2021
We propose a novel optical path assignment algorithm that reduces the power consumption of MC-EDFAs in SDM photonic nodes. We simulate efficient path assignment and experimentally demonstrate its power-saving relative to the conventional algorithm.
Cited by 2
Senfar Wen, Yu‐Hsiung Lin · 2013
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Par, SLJDE Steven van de, Ten Kate, W RTh, Kohlrausch, AG Armin et al. · TU/e Research Portal (Eindhoven University of Technology) · 1994
<p>A method is proposed to achieve full-frequency-range three-channel (left, right, and center) sound reproduction in systems that have only two full-range sound channels and some band-limited commentary channels. The low-frequency part of the center signal, which matches the bandwidth of the commentary channels, is added to the (multilingual) speech signals in each of the commentary channels. The remaining high-frequency part is added in the left and right channels as in conventional mixdowns. Sound reproduction of this signal by a conventional two-channel receiver remains unaltered. The low-frequency part of the center signal is mixed to the left and right signals together with the speech once the user has selected a commentary channel. Three-channel reproduction is obtained by routing the selected commentary channel to a central loudspeaker. Listening tests revealed that sound reproduction according to the proposed scheme could not be distinguished from original three-channel reproduction. This scheme can be applied to proposed standards such as D2MAC and MPEG2.</p>
Cited by 0
Wei Chen, Xianguo Zhang, Yonghong Tian et al. · 2012
Background modeling is an important pre-processing step for object detection in surveillance video analysis systems. Recently, it has been proved to be useful for high-efficiency surveillance video coding. In existing works, the modeling background frame often needs to be high-quality encoded so as to achieve a large bit-rate saving. However, the high-quality background frame requires lots of bits in the code stream, so it is infeasible to update the background frame too frequently. Therefore, a better bit-allocation method is desirable to facilitate in-time background updating and bit-saving background coding. In this paper, we firstly build up a background updating model from a detailed analysis of results on surveillance video. Following this, we propose a bit-saving and quality-maintaining background frame coding method. In our method, the background frame can be updated more timely, consequently leading to the better coding efficiency. Experimental results show that our method can achieve more than 15% bit-rate decrease compared with three state-of-art methods.
Cited by 3
Dongyun Kam, Myeongji Yun, Sunwoo Yoo et al. · 2025
Low bit-precisions and their bit-slice sparsity have recently been studied to accelerate general matrix-multiplications (GEMM) during large-scale deep neural network (DNN) inferences. While the conventional symmetric quantization facilitates low-resolution processing with bit-slice sparsity for both weight and activation, its accuracy loss caused by the activation’s asymmetric distributions cannot be acceptable, especially for largescale DNNs. In efforts to mitigate this accuracy loss, recent studies have actively utilized asymmetric quantization for activations without requiring additional operations. However, the cuttingedge asymmetric quantization produces numerous nonzero slices that cannot be compressed and skipped by recent bit-slice GEMM accelerators, naturally consuming more processing energy to handle the quantized DNN models.To simultaneously achieve high accuracy and hardware efficiency for large-scale DNN inferences, this paper proposes an Asymmetrically-Quantized bit-Slice GEMM (AQS-GEMM) for the first time. In contrast to the previous bit-slice computing, which only skips operations of zero slices, the AQS-GEMM compresses frequent nonzero slices, generated by asymmetric quantization, and skips their operations. To increase the slicelevel sparsity of activations, we also introduce two algorithm-hardware co-optimization methods: a zero-point manipulation and a distribution-based bit-slicing. To support the proposed AQS-GEMM and optimizations at the hardware-level, we newly introduce a DNN accelerator, Panacea, which efficiently handles sparse/dense workloads of the tiled AQS-GEMM to increase data reuse and utilization. Panacea supports a specialized dataflow and run-length encoding to maximize data reuse and minimize external memory accesses, significantly improving its hardware efficiency. Numerous benchmark evaluations show that Panacea outperforms existing DNN accelerators, e.g., $1.97 \times$ and $3.26 \times$ higher energy efficiency, and $1.88 \times$ and $2.41 \times$ higher throughput than the recent bit-slice accelerator Sibia and the SIMD design, respectively, on OPT-2.7B, while providing better algorithm performance with asymmetric quantization.
Cited by 3
Bhawna Rawat, Poornima Mittal · ACM Transactions on Design Automation of Electronic Systems · 2023
The decreasing operational voltage and scaled technology node for memory designing has widened the gap between two crucial parameters for an SRAM – delay and power. As the demand for internet of things is increasing, the need for round the clock connectivity is increasing. This mandates designing a cell with a capability to switch between low power and high speed operation. Thus, this paper presents the design of dual mode operational 7T cell that can switch between single port and dual port configuration. The proposed reconfigurable cell can operate as single port or dual port cell single ended 7T cell. The reconfigurability in the cell is realized using control signals. The noise stability of the bit cell is obtained to be 333, 333, and 470 mV for read, hold, and write modes, respectively. The robustness of the cell against temperature variation, process variation and voltage variation is also analyzed. The performance variation in each parameter will not have a dramatic impact as it is within manageable limit. Its write time is 0.14 ns, while 5 ps are required for a successful read operation. The dual port configuration of the cell supports pipelining and thus operates faster than its single port configuration.
Cited by 9
Wen-Jun Cao, Dongming Mei, Yang Guo et al. · Measurement · 2025
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Par, van de, SLJDE Steven, Kate, ten, WRTh, Kohlrausch, AG Armin et al. · Data Archiving and Networked Services (DANS) · 1994
Cited by 0
Tanaka, Tanzawa, Takéuchi · 1997
Cited by 14