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About 571 papers for “cache coherence protocols”
Shen, Xiaowei, 1966- · DSpace@MIT (Massachusetts Institute of Technology) · 2000
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Cited by 0Open access
Jason F. Cantin, Mikko H. Lipasti, James E. Smith · 2004
Cited by 38
Homayoon Akhiani, Damien Doligez, Paul Harter et al. · 1999
Cited by 0
Michel Dubois · 1997
In this article we present a comprehensive survey of various approaches for the verification of cache coherence protocols based on state enumeration, (symbolic) model checking, and symbolic state models. Since these techniques search the state space of the protocol exhaustively, the amount of memory required to manipulate the state information and the verification time grow very fast with the number of processors and the complexity of the protocol mechanisms. To be successful for systems of arbitrary complexity, a verification technique must solve this so-called state space explosion problem. The emphasis of our discussion is on the underlying theory in each method of handling the state space explosion problem, and formulating and checking the safety properties (e.g., data consistency) and the liveness properties (absence of deadlock and livelock). We compare the efficiency and discuss the limitations of each technique in terms of memory and computation time. Also, we discuss issues of generality, applicability, automaticity, and amenity for existing tools in each class of methods. No method is truly superior because each method has its own strengths and weaknesses. Finally, refinements that can further reduce the verification time and/or the memory requirement are also discussed.
Cited by 0
Perko, Tilen · Repository of the University of Ljubljana (University of Ljubljana) · 2025
Namen diplomske naloge je implementacija dveh programov za simulacijo delovanja vohljalnega protokola MSI in protokola na osnovi imenika, ki poročata tudi o statistiki zadetkov in zgrešitev v predpomnilniku in izpisujeta stanja protokolov. Pri vohljalnem protokolu MSI program izpisuje vrednosti glavnega pomnilnika in vseh predpomnilnikov po vsaki operaciji branja ali pisanja, ki jih prebere iz zunanje datoteke. Pri protokolu na osnovi imenika pa poleg tega izpisuje tudi vrednosti imenika po vsaki operaciji branja ali pisanja. Protokol MSI je bolj primeren v sistemih s simetričnim skupnim pomnilnikom, protokol na osnovi imenika pa sicer v sistemih s porazdeljenim skupnim pomnilnikom, a v tej nalogi je implementirana osnovna verzija za sisteme s simetričnim skupnim pomnilnikom.
Cited by 0Open access
Iosr Journals, Kaushik Roy, Pavan Kumar S.R et al. · Figshare · 2015
Cited by 1Open access
Rajeev Joshi, Leslie Lamport, John Matthews et al. · Formal Methods in System Design · 2003
Cited by 55
Iosr Journals, Kaushik Roy, Kumar S.R Pavan et al. · Figshare · 2015
In this new age of technology, not only the software but also the computer architecture has been evoluted to support those softwares. The main motive of evolution of architecture day by day is to make the system faster. One of the major steps in this journey of evolution is the multi-core processor architecture. In a multi-core processor system, each core has its own cache module where they are sharing the same memory unit. For that reason, one block in one cache gets invalidate when the same block is updated into any other cache and this is called cache coherence problem. To overcome this, there are lot of research works are going on and the outcome rules or techniques are called cache coherence protocols.The main objective of this paper is to collect all those research works together and represent them in an easy way, so that we could understand their techniques to overcome the particular problem. Here it is presented a comprehensive study of those cache coherence protocols with their pros and cons. I. Introduction In the complex multilevel cache level architecture to bind the cache coherence protocol complexity we need to track the coherence information across all the levels but this leads implausible cost problem. To empower our future processors we need to embed more number of cores per chip multiprocessor. But during this we must face the off chip bandwidth wall, again to overcome this we can use a large on chip cache but because of plain large capacities of hardware the fast access could not be achieved. So commercially it is used three level cache architecture where two are used to maintain private data being closer to processor and the last one shared among cores. Have large number of cores might be helpful in some most of the cases but at the same time it is unachievable to rely on broadcast-based coherence protocols. II. Comprehensive Studies
Cited by 1Open access
Chung, Do-Young · SHAREOK (University of Oklahoma; Oklahoma State University; Central Oklahoma University) · 2014
Cited by 0Open access
Martina Camaioni, Yann Herklotz, Tz-Ching Yu et al. · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 2026
Verifying cache coherence protocols is a notoriously difficult problem. At the intersection between distributed protocol and computer architecture, it has long served as a premier target for formal methods. Current verification approaches hinge on the challenging discovery of large global inductive invariants. This paper introduces an alternative proof strategy that tames the complexity through two main contributions: protocol decomposition and a framework of local invariants.
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C. Smith, David Lars Chaiken, David Lars Chaiken · 1990
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both network traffic and average memory access latency. However, cachebased systems must address the problem of cache coherence. This thesis presents the results of the search for a cache coherence solution for Alewife, a large-scale multiprocessor being built at MIT. The research focuses on coherence protocols that use a directory, a list of cached copies of data, to avoid the need for a system-wide broadcast mechanism. The structure and the implementation of a number of coherence schemes are evaluated with coupled and decoupled simulation techniques. In addition to comparing the protocols in terms of hardware overhead and performance, the thesis reports on the experience gained by implementing several different schemes in ASIM, the Alewife machine simulator. The protocol search reaches two major conclusions: First, by using system-level optimizations, it is possible to use caches to build la...
Cited by 0
Fernández Pascual, Ricardo · Digitum: Institutional Repository of the University of Murcia (University of Murcia) · 2007
Abstract: \nWe propose a way to deal with transient faults in the interconnection network of many-core CMPs that is different from the classic approach of building a fault-tolerant interconnection network. In particular, we provide fault tolerance mechanisms at the level of the cache coherence protocol so that it guarantees the correct execution of programs even when the underlying interconnection network does not deliver all messages correctly. This way, we can take advantage of the different meaning of each message to achieve fault tolerance with lower overhead than at the level of the interconnection network, which has to treat all messages alike with respect to reliability. \nWe design several fault-tolerant cache coherence protocols using these techniques and evaluate them. This evaluation shows that, in absence of faults, our techniques do not increase significantly the execution time of the applications and their major cost is an increase in network traffic due to acknowledgment messages that ensure the reliable transference of ownership between coherence nodes, which are sent out of the critical path of cache misses. In addition, a system using our protocols degrades gracefully when transient faults actually happen and can support fault rates much higher than those expected in the real world with only a small performance degradation. \nResumen: \nSe proponen una forma de tratar con los fallos transitorios en la red de interconexión de un CMP con gran número de núcleos que es diferente del enfoque clásico basado en construir una red de interconexión tolerante a fallos. En particular se proporcionan mecanismos de tolerancia a fallos al nivel del protocolo de coherencia. De esta forma, se puede aprovechar el conocimiento que el protocolo tiene sobre el significado de cada mensaje para obtener tolerancia a fallos con menor sobrecarga que en el nivel de red, que tiene que tratar todos los mensajes idénticamente. \nEn la tesis se diseñan y evalúan varios protocolos de coherencia utilizando estas técnicas. Los resultados muestran que, cuando no hay fallos, nuestras técnicas no incrementan significativamente el tiempo de ejecución de las aplicaciones y su mayor coste es un incremento en el tráfico de red. Además, un sistema que use nuestros protocolos soporta tasas de fallos mucho mayores que las esperadas en circunstancias realistas y su rendimiento se degrada gradualmente cuando ocurren los fallos.
Cited by 0Open access
أنيس القردوح, عبدالحميد الكواش, عبدالمحسن البنداق · Journal of Pure & Applied Sciences · 2022
The cache coherence problem is the challenge of keeping multiple cache synchronized when one of the processors update its local copy of data which is shared among multiple cache. This paper discusses several different varieties of cache coherence protocols including with their pros and cons, and using simulation technique it will address this problem and compare between two protocols that use to solve it: Directory-based protocol and Snooping protocol. Simulation results have shown that snooping based systems are appropriate for high bandwidth systems while directory-based cache coherence protocols are suitable for lower bandwidth systems.
Cited by 0Open access
Chung, In-Suk · SHAREOK (University of Oklahoma) · 2014
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Jerónimo Nájera, Luis Gómez · ACM SIGCSE Bulletin · 1994
Several protocols have been proposed in order to solve the cache coherence problem. In all cases, it is very difficult to understand how each algorithm works. The tool ToCCata has been designed and developed to graphically show the dynamic behavior of generic cache coherence algorithms. ToCCata can be used for pedagogical or demonstration purposes.
Cited by 0
Nguyen, Quan Minh (Scientist in electrical engineering and computer science) Massachusetts Institute of Technology · DSpace@MIT (Massachusetts Institute of Technology) · 2016
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
Cited by 0Open access
Giorgio Delzanno · 2000
. We propose a new method for the verication of parameterized cache coherence protocols. Cache coherence protocols are used to maintain data consistency in multiprocessor systems equipped with local fast caches. In our approach we use arithmetic constraints to model possibly innite sets of global states of a multiprocessor system with many identical caches. In preliminary experiments using symbolic model checkers for innite-state systems based on real arithmetics (HyTech [HHW97] and DMC [DP99]) we have automatically veried safety properties for parameterized versions of widely implemented write-invalidate and writeupdate cache coherence policies like the Mesi, Berkeley, Illinois, Firey and Dragon protocols [Han93]. With this application, we show that symbolic model checking tools originally designed for hybrid and concurrent systems can be applied successfully to a new class of innite-state systems of practical interest. 1 Introduction In a shared-memory multipro...
Cited by 0
Jianhua Li, Liang Shi, Qingan Li et al. · IEEE Transactions on Parallel and Distributed Systems · 2013
For chip multiprocessor systems (CMPs), the interference on shared resources such as on-chip caches typically leads to unbalanced progress among threads. Because of the inherent synchronization primitives, such as barriers and locks, cores running fast threads have to waste precious cycles to wait for cores with slow progress, which leads to performance and energy inefficiency. For the purpose of improving performance and reducing energy consumption, this paper proposes to adapt the cache coherence policy for threads according to their delay-tolerant levels. Specifically, this paper proposes Thread progrEss Aware Coherence Adaption (TEACA) which utilizes the thread progress information as hints for coherence adaption. TEACA dynamically utilize the memory system statistics to estimate the progress of threads. Based on the estimated thread progress information, TEACA categorizes threads into leader threads and laggard threads. The thread categorization decisions are then leveraged for efficient coherence adaption on CMP systems supporting hybrid coherence protocols. Experimental results show that, on a 64-core CMP system, TEACA outperforms directory protocol in application execution time and a recently proposed hybrid protocol in both application execution time and energy dissipation.
Cited by 5
Sinisa Srbljic Zvonko, Zvonko G. Vranesic, Michael Stumm et al. · 2007
Key words: Cache coherence, distributed shared memory, memory access behavior, analytical performance prediction, performance evaluation, dynamic hybrid protocols. In a modern shared memory multiprocessor, it is possible to support more than one protocol for maintaining cache coherence. Possible candidates might be based on the Write-Back/Invalidate, Write-Through/Invalidate, and Write-Update protocols. Hybrid protocols allow the use of different protocols for different data blocks, and dynamic hybrid protocols additionally allow for changes in the choice of protocol during the execution of an application. In this paper, we introduce a set of analytical models for predicting the performance of parallel applications under various cache coherence protocol assumptions. These models can be used at compile time to determine which protocols are to be used for which data blocks, and also to determine when to change protocols in the case of dynamic protocols. Although we focus on tightly-coupl...
Cited by 0
Zainab Alwaisi, Michael Opoku Agyeman · 2017 Intelligent Systems Conference (IntelliSys) · 2017
Cache coherence protocols have significant impact on the performance of distributed and centralized shared-memory of a multiprocessor, and they are required for maintaining data consistency in a chip-multiprocessor system (CMP). Thus, cache protocols play a major role in improving the performance of multiprocessor systems. Specifically, an efficient cache coherence protocol should ensure the updating of processor data, broadcasting valid data other processors and main memory to prevent the main memory or other processors from loading invalid values. To address this issue of efficiency in maintaining cache coherency, several contribution, such as using invalidation-based protocols with a write through cache coherence, have been made over the past years. This paper presents an overview of emerging cache coherence protocols which aim at improving the performance of CMPs. Furthermore, an example of using an invalidation-based protocol with a write through for solving cache's coherency is provided.
Cited by 12