Introduction Low power VLSI design can be achieved at various levels of the design abstraction from algorithmic and system levels down to layout and circuit levels (see Figure 1). Power optimization techniques at the system, architectural (behavioral) design level, register-transfer (RT) level, physical design level, and the circuit level have been addressed by researchers in the past. Logic synthesis however, is an important part of the design cycle for a digital system. This means that in order to minimize power effectively, power has to be considered during logic synthesis and optimization. Logic synthesis provides the automatic synthesis of gate-level netlists, minimizing some objective function subject to various constraints. The goal, in general is to obtain a minimum area circuit subject to a given delay requirement. Example inputs to a logic synthesis system include two-level logic representation, multi-level Boolean networks, finite state machines and technology mapped circu

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Uncertainty-Aware Circuit Optimization

Xiaoliang Bai University, Xiaoliang Bai, Philip N. Strenski · 2002

A5#(+(+BC/=D8;53-3:FE:&lt;/HG(9I#:&lt;J=I#D:&lt;/=.AK9GL 8D*40O5PJQ,R-5SD9G(+(+2TIPJ=:&lt;/=:+IG(4U9G/=K;.#&gt;V@MK;:+IHKWRX,J=*YGZ.&quot;,BIG(+(F5#3 [ @\\G(F(+]^:+8_/=K5`.&quot;(FGIHa_K:+./=,EJHG*`bdce,@A5#L ;:+IHKWRX,J=*YGZ.&quot;,BIG( 35#.&quot;:+E8-K;G.0O5#5#8h/=KJ=,D;EKh*iG8DRjGIP/=DJ=:+8;E&gt;*iG82kD;8I#5PJ&quot;/HG:+8/=:+5#. I#GD;.&quot;5\\/=K5#.&quot;5\\IGJ=57RjD;(+(&lt;2-G(+:FE8;53-35#(FG#2./=,l.&quot;UJ=5G3m,D/bon89GI#I#DJHGB IP:F5P.l:+8pU;GJHG.&quot;:&lt;/=:+I4UJ=53:+IP/=:+,8;.#&gt;?I#(+,I7aQ.&quot;(+5P@N&gt;?*-,35#(&lt;B/=,BK9GJH3@\\GJ=5 IP,J&quot;J=5#(FG/=:+,8q&gt;N./HG/=:FIr/=:+*-:+8;EsG.&quot;.&quot;D*-U/=:+,8.fG893t*iG8DRuGIP/=DJ=:+8;E LGJ=:FG/=:F,8;.gG(+()IGD.&quot;5`/=K;5QUO5PJ&quot;RX,J=*iG8I#5f/=,vLGJ&quot;2sRwJ=,*xUJ=5#3:+IPB /=:+,8qbmy:+*-U(F5k./HG/=:+./=:+IG(UJ=:+8;I#:+U;(+5#.l/=5P(F(D.z/=K;G/l/=K5mLGJ=:FG/=:+,8 ,Rz/=K5g(+:+*-:&lt;/=:+8;E{.&quot;(wGI7a^:+.h(FGJ=E5PJh@MK5#8^/=K;5|K;5#:+EK/4,Rz/=K;5-@\\G(F( :+.MEJ=5#G/=5PJbA&apos;z(&lt;/=K;,D;EKg/=K;5z@\\G(+(q*iG2i0O5l/=K5l,U/=:+*4D;*}.&quot;,(+D/=:+,8 :&lt;RV/=K;5r./HG/=:FIQ/=:+*-:+8;E^UJ=53:+IP/=:+,8.|@A5PJ=5{UO5PJ&quot;Rj5#I7/&gt;e:+8t/=K;5QUJ=5#.B 5P8;I#5l,RoD8;I#5PJ&quot;/HG:+8/~2-:+8|/=:+*-:+8;EkG893i*iG8DRjGIP/=DJ=:F8E&gt;:&lt;/\\*iG#2-8;, (+,8;E57JM0O5z/=K;5)0O5#./\\IHK;,:+I#5b!K;5eGUU;(+:+IG/=:+,8g,RqRj,J=*iG(O*iG/=K5PB *iG/=:+IG(,U/=:F*-:+G/=:+,84:+8k/&quot;JHG8;.&quot;:+./=,J1.&quot;:+#:+8EN:F8IPJ=5G.&quot;5#./=K;5!K5#:+EK/ ,R/=K;5N@\\G(F(u&gt;/=KD;.M5PGIP5PJ=09G/=:F8E-/=K;5VUJ=,0;(+5#*`bM!K5PJ=5m:+.eG(+.&quot;,|G UJHGIP/=:+IG(*iG/&quot;/=5PJ?/=K9G/&amp;.&quot;IHK;5P*iG/=:+IJ=5#./&quot;J=D;IP/=DJ=:+8;E)3,@M8;./&quot;J=5#G*T:F8 /=K5e35#.&quot;:+E8|*-5P/=K;,3,(+,E2i:+.!5G.&quot;:+5PJ\\/=,kI#,8;I#5#:+L J=:+8;E)3,@M8;...

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Capillary Discharge Circuit Optimization

Vrba, Pavel · Digital Repository (National Repository of Grey Literature) · 2003

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Uncertainty-aware circuit optimization

Xiaoliang Bai, Chandu Visweswariah, Philip N. Strenski · Proceedings - ACM IEEE Design Automation Conference · 2002

Almost by definition, well-tuned digital circuits have a large number of equally critical paths, which form a so-called "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inaccuracies in parasitic predictions, clock slew, model-to-hardware correlation, static timing assumptions and manufacturing variations all cause the performance to vary from prediction. Simple statistical principles tell us that the variation of the limiting slack is larger when the height of the wall is greater.Although the wall may be the optimum solution if the static timing predictions were perfect, in the presence of uncertainty in timing and manufacturing, it may no longer be the best choice. The application of formal mathematical optimization in transistor sizing increases the height of the wall, thus exacerbating the problem. There is also a practical matter that schematic restructuring downstream in the design methodology is easier to conceive when there are fewer equally critical paths. This paper describes a method that gives formal mathematical optimizers the incentive to avoid the wall of equally critical paths, while giving up as little as possible in nominal performance. Surprisingly, such a formulation reduces the degeneracy of the optimization problem and can render the optimizer more effective. This "uncertainty-aware" mode has been implemented and applied to several high-performance microprocessor macros. Numerical results are included.

Cited by 9

Process multi-circuit optimization

Arun N. Lokanathan, Jay Brockman · 1998

This paper describes the implementation of a concurrent methodology for integrated circuit optimization that spans the fabrication process design and circuit design disciplines. Results from this methodology show substantial performance gains as compared to a separate process/circuit optimization and a substantial time savings over an “all-at-once” combined optimization.

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Reliability aware circuit optimization

Diana Marculescu, Kai–Chiang Wu · 2011

Due to current technology scaling trends such as shrinking feature sizes and decreasing supply voltages, nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors). Logical masking, electrical masking, and latching-window masking, which used to effectively prevent transient events in logic circuits from being latched into memory elements, are weakened with continuous scaling trends. Therefore, soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits. Unless explicitly dealt with, the soft error rate (SER) of logic is expected to be comparable to that of unprotected memories. Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, is becoming a critical challenge for temporal reliability concerns in nanoscale designs. In the literature, NBTI-induced PMOS aging has been demonstrated to be an exponential function of oxide thickness and operating temperature. With aggressive technology scaling trends such as thinner gate oxide without proportional downscaling of supply voltage, the need of an optimization flow considering NBTI effects during early design stages emerges. This dissertation research presents low-cost methodologies for reducing circuit SER and mitigating NBTI-induced performance degradation. For SER reduction, three approaches based on redundancy addition and removal (RAR), selective voltage scaling (SVS), and clock skew scheduling (CSS) are proposed to provide compounding improvements. For NBTI mitigation, joint logic restructuring (LR) and pin reordering (PR) are exploited to combat performance degradation, with path sensitization explicitly considered. Finally, the recovery mechanism of NBTI and the use of reverse body bias are explored to achieve lifetime exten- sion for power-gated circuits.

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Circuit Switched Fallback Optimization

Xincheng Zhang · 2017

Circuit switched fallback (CSFB) addresses the requirements of the first phase of the evolution of mobile voice services, which began on a commercial scale in 2011. CSFB is the solution to the reality of mixed networks today and throughout the transition to ubiquitous all-LTE networks in the future phases of LTE voice evolution. Usually, the operator may deploy LTE with 3GPP CSFB solution across LTE coverage area. In CSFB, whenever an LTE handset generates or receives a voice call it is automatically transferred to the 2G/3G networks. The key point from CSFB view is the SGs interface between MSC and mobility management entity (MME) that SGs interface connects the MSC/VLR and the serving GPRS support node and MME (SGSN-MME). This interface is used for registration in the MSC/VLR of the UE by performing combined procedures, to page the UE on behalf of the MSC/VLR and to convey CS-related services.

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Circuit Optimization Predicts Dynamic

Networks For Chemosensory, Nematode Caenorhabditis Elegans, Nathan A. Dunn et al. · 2003

The connectivity of the nervous system of the nematode Caenorhabditis elegans has been described completely, but the analysis of the neuronal basis of behavior in this system is just beginning. Here, we used an optimization algorithm to search for patterns of connectivity sufficient to compute the sensorimotor transformation underlying C. elegans chemotaxis, a simple form of spatial orientation behavior in which turning probability is modulated by the rate of change of chemical concentration.

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Circuit Synthesis and Resource Optimization

Daniele Cuomo · Springer theses · 2024

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Rotation-inspired circuit cut optimization

Gideon Uchehara, Tor M. Aamodt, Olivia Di Matteo · arXiv (Cornell University) · 2022

Recent works have demonstrated that large quantum circuits can be cut and decomposed into smaller clusters of quantum circuits with fewer qubits that can be executed independently on a small quantum computer. Classical post-processing then combines the results from each cluster to reconstruct the output of the original quantum circuit. However, the runtime for such hybrid quantum-classical algorithms is exponential in the number of cuts on a circuit. We propose Rotation-Inspired Circuit Cut Optimization (RICCO), an alternative method which reduces the post-processing overhead of circuit cutting, at the cost of having to solve an optimization problem. RICCO introduces unitary rotations at cut locations to rotate the quantum state such that expectation values with respect to one set of observables are maximized and others are set to zero. We demonstrate practical application of RICCO to VQE by classically simulating a small instance of VQE and comparing it to one of the existing circuit-cutting methods.

Cited by 1Open access

Circuit Optimization for Universality Transformation

Yasuaki Nakayama, Yuki Takeuchi, Seiseki Akibue · arXiv (Cornell University) · 2026

It is known that a computationally universal gate set $\{H,CCZ\}$ can be transformed to a strictly universal one $\{Λ(S), H\}$ using one maximally imaginary state $|+i\rangle$ and non-imaginary ancillary qubits. We succeed this transformation with a shorter circuit that eliminates non-imaginary ancillary qubits. We further extend this to the continuous gate-set setting, showing that any multi-qubit unitary can be exactly generated by real single-qubit unitary gates, $CCZ$ gates and $|+i\rangle$.

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Optimization driven quantum circuit reduction

Bodo Rosenhahn, Tobias J. Osborne, Christoph Hirche · New Journal of Physics · 2025

Abstract Implementing a quantum circuit on specific hardware with a reduced available gate set is often associated with a substantial increase in the length of the equivalent circuit. This process is also known as transpilation and due to decoherence, it is mandatory to keep quantum circuits as short as possible, without affecting functionality. In this work we propose three different transpilation approaches, based on a localized term-replacement scheme, to substantially reduce circuit lengths while preserving the unitary operation implemented by the circuit. The first variant is based on a stochastic search scheme, and the other variants are driven by a database retrieval scheme and a machine learning based decision support. We show that our proposed methods generate short quantum circuits for restricted gate sets, superior to the typical results obtained by using various qiskit and Berkley quantum synthesis toolkit optimization levels. Our method can be applied to different gate sets and scales well with an arbitrary number of qubits.

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Circuit-Layout Co-Optimization for . . .

Vyacheslav V. Rovner · 2010

The manufacturability benefits of restricted design style have long been recognized in the implementation of SRAM and FPGA circuits. However, the ASIC community has shied away from layout restrictions for the fear of stifling designers’ creativity and creating an inefficient area, and thus cost, product. Nevertheless, as the design features required began to approach nanometer-scale dimensions, the inability to guarantee the process window across the entire design space has led to substantial yield losses and raised questions about existing design assumptions. This dissertation presents a regular fabric based design methodology that embraces a restricted layout style required for enabling successful manufacturing of the sub-32 nm technology nodes. Unlike the vast number of layout geometries allowed by design rules, the regular design fabric forms a new interface between the process and design communities to succinctly communicate the set of permitted layout constructs. While the manufacturability benefits are provided by this new interface, an area efficient implementation

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Circuit Optimization for Universality Transformation

Yasuaki Nakayama, Yuki Takeuchi, Seiseki Akibue · arXiv (Cornell University) · 2026

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Quantum circuit for spatial optimization

Nikolay Raychev · International Journal of Scientific and Engineering Research · 2015

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