Quinn Jacobson, Steve Bennett, Nikhil Sharma et al. · 1997
The Multiscalar architecture executes a single sequential program following multiple flows of control. In the Multiscalar hardware, a global sequencer, with help from the compiler, takes large steps through the program's control flow graph (CFG) speculatively, starting a new thread of control (task) at each step. This is inter-task control flow speculation. Within a task, traditional control flow speculation is used to extract instruction level parallelism. This is intra-task control flow speculation. This paper
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Artur Kauser, Dirk Grunwald, Srilatha Manne et al. · 1998
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Srilatha Manne, Dirk Grunwald · 1999
Branch prediction enables microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although speculative execution is essential for increasing the instructions per cycle (IPC), it does come at a cost. A large amount of unnecessary work results from wrong-path instructions entering the pipeline due to branch misprediction. Results generated with an event driven cycle level simulator on a 4-way issue pipeline and various branch predictors show that there are sometimes twice as many instructions fetched as committed. The instruction overhead from speculative execution will increase in the future as processors use more aggressive speculation and wider issue widths [53].
In this thesis, an innovative method for power reduction is presented which, unlike previous work that sacrificed flexibility or performance, reduces power in high-performance microprocessors without impacting performance. In particular, a hardware mechanism called PIPELINEGATING is introduced to control rampant speculation in the pipeline. Depending on the number of probable mispredicted branches in the pipeline, P IPELINEGATING stops instructions from entering the pipeline. PIPELINEGATING is evaluated with dynamic and static mechanisms for determining when a branch is likely to mispredict, and for stopping wrong-path instructions from entering the pipeline. Results show a measurable decrease in wrong-path instructions with negligible performance loss ( a 1%). Best of all, even in programs with a high branch prediction accuracy, performance does not noticeably degrade. The analysis indicates that there is little risk in implementing this method in existing processors since it does not impact performance and benefits energy reduction.
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Dirk Grunwald, Artur Klauser, Srilatha Manne et al. · 2002
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and only committed if the original predictions were correct. There are a number of other ways that processor resources could be used, such as threading or eager execution. As the use of speculation increases, we believe more processors will need some form of speculation control to balance the benefits of speculation against other possible activities. Confidence estimation is one technique that can be exploited by architects for speculation control. In this paper, we introduce performance metrics to compare confidence estimation mechanisms, and argue that these metrics are appropriate for speculation control. We compare a number of confidence estimation mechanisms, focusing on mechanisms that have a small implementation cost and gain benefit by exploiting characteristics of branch predictors, such as clustering of mispredicted branches. We compare the performance of the different confidence estimation methods using detailed pipeline simulations. Using these simulations, we show how to improve some confidence estimators, providing better insight for future investigations comparing and applying confidence estimators.
Cited by 67
Aristides Efthymiou, Jim Garside · 2003
Pipelining is a common method for improving the throughput of a system, especially when the majority of the processing is sequential. Unfortunately when the sequentiality is broken, a pipelined system suffers additional delay and, most importantly for this work, energy waste which is roughly proportional to the pipeline depth. Standard pipelines cannot be modified once they are built so their depth is fixed. This paper proposes a method that allows the dynamic adaptation of the structure of an asynchronous pipeline, so that pipeline stages can be merged and split at run-time, allowing greater flexibility. It is based on novel latch controllers that can be configured dynamically as 'normal' or 'collapsed', i.e. keeping their latches permanently transparent. Using these controllers a model of AMULET3 was designed that is capable of changing its pipeline depth dynamically when branches are anticipated, in order to alleviate the energy loss when the branch finally arrives.
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Ranganathan, Nitya · Texas ScholarWorks (Texas Digital Library) · 2009
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Aristides Efthymiou Jim, Jim D. Garside · 2007
Pipelining is a common method for improving the throughput of a system, especially when the majority of the processing is sequential. Unfortunately when the sequentiality is broken, a pipelined system suffers additional delay and, most importantly for this work, energy waste which is roughly proportional to the pipeline depth. Standard pipelines cannot be modified once they are built so their depth is fixed. This paper proposes a method that allows the dynamic adaptation of the structure of an asynchronous pipeline, so that pipeline stages can be merged and split at run-time, allowing greater flexibility. It is based on novel latch controllers that can be configured dynamically as `normal' or `collapsed', i.e. keeping their latches permanently transparent. Using these controllers a model of AMULET3 was designed that is capable of changing its pipeline depth dynamically when branches are anticipated, in order to alleviate the energy loss when the branch finally arrives.
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Quinn Jacobson, S. Bennett, Nalin Kumar Sharma et al. · 2002
The multiscalar architecture executes a single sequential program following multiple flows of control. In the multiscalar hardware, a global sequencer with help from the compiler takes large steps through the program's control flow graph (CFG) speculatively, starting a new thread of control (task) at each step. This is inter-task control flow speculation. Within a task, traditional control flow speculation is used to extract instruction level parallelism. This is intra-task control flow speculation. This paper focuses on mechanisms to implement inter-task control flow speculation (task prediction) in a multi-scalar implementation. This form of speculation has fundamental differences from traditional branch prediction. We look in detail at the issues of prediction automata, history generation and target buffers. We present implementations in each of these areas that offer good accuracy, size and performance characteristics.
Cited by 67
K. Luo, M. Franklin, S. Mukherjee et al. · 2002
Simultaneous Multithreading (SMT) is a technique that permits multiple threads to execute in parallel within a single processor. Usually, an SMT processor uses shared instruction queues to collect instructions from the different threads. Hence, an SMT processor's performance depends on how the instruction fetch unit fills these instruction queues. On each cycle the fetch unit must judiciously decide which threads to fetch instructions from. This paper proposes a new instruction fetch scheme that uses both fetch prioritizing and fetch gating for SMR processors. Fetch prioritizing sets up fetch priority for each thread based on the number of unresolved low-confidence branches from the thread, while fetch gating prevents fetching from a thread once it has a stipulated number of out-standing low-confidence branches. Based on the fetch priority of each thread, our fetch scheme finds threads that are most likely to be in their correct paths. This improves the overall throughput of an SMT processor by reducing the number of wrong-path instructions in the pipeline. Our experimental evaluation shows that, on the average, our fetch scheme provides 14.9% speedup over ICOUNT, which is the best fetch policy reported so far for SMT.
Cited by 53
Morgan, Josh L. · PhilPapers (PhilPapers Foundation)
Most of us are familiar with reports of lab animals that, when presented with a lever that provides opioids or cocaine, will press the lever over and over at the expense of food and water (Deneau, Yanagita, and Seevers 1969; Weeks 1962; Deroche-Gamonet, Belin, and Piazza 2004). This paradigm has not only been used by researchers to study drug effects but also entered the culture as an anti-drug parable. In the most famous of these types of studies (Olds and Milner 1954) the lever wasn't delivering drugs, but direct electrical stimulation to the brain’s reward circuits. This research inspired a genre of 'wireheading' (Niven 1969); speculative fiction in which humans build technologies that allow them to directly manipulate reward systems. The general theme of these stories is that self-stimulation leads to loss of agency and social decay. The framework of social distaste does not do justice to the biological, technical, and philosophical implications of an intelligent agent finding ways to subvert its own control system. When we consider the goals and relationships of genomes, nervous systems, social systems, and artificial intelligence, we find that the subversive behavior of hacking your own reward system is not an aberration. Rather, reward hacking it is the default behavior of both evolved and engineered intelligent agents and is overcome only by constant innovation and effort on the part of control systems. The more capabilities available to an intelligent agent, the more likely it is to find ways to hack its own reward system. At the extreme, an organism smart enough to gain complete control over its own reward system, i.e. build itself a golden lever to press, should be expected to completely cease functioning. The seemingly inevitable non-functional endpoint to increasing the capabilities of an intelligent agent is the self-control paradox. By asking whose goals are being subverted when reward systems are hacked, we can better understand our relationship to our genome, to each other, and to artificial intelligence.
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Ulrich Sigmund, Theo Ungerer · Zenodo (CERN European Organization for Nuclear Research) · 2001
A simultaneous multithreaded (SMT) processor is able to issue and execute instructions from several threads simultaneously. A SMT processor reaches its highest performance, when all issue slots are utilized by non-speculative instructions provided that the workload is sufficient. SMT processors are able to utilize their resources by executing instructions of multiple threads simultaneously, whereas single-threaded processors fill their resources with highly speculative instructions that must frequently be discarded due to misspeculations. Consequently, we explore speculation control in SMT processor models with the target to increase performance by restricting the number of in-flight speculative instructions. We vary the sizes of internal buffers, the instruction fetch bandwidth, the instruction selection strategies and branch prediction models with the target to increase performance of the simulated SMT processor models. Our results show (1) that retirement buffer sizes of 16 or 32 entries increase performance compared to smaller and to larger buffer sizes, (2) that the instruction fetch bandwidth can be decreased to two times four instructions per cycle without performance loss even for eight threaded eight issue processor models, (3) that an instruction selection strategy that discriminates speculative instructions in the fetch, decode, issue, and dispatch stages may increase overall performance, and (4) that a highly multithreaded processor with a sufficient workload may do without a branch prediction.
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Neelakantam, Naveen · Illinois Digital Environment for Access to Learning and Scholarship (University of Illinois at Urbana-Champaign) · 2012
This dissertation introduces the atomic region as a novel compiler abstraction which eases \nthe development of speculative compiler optimizations. As this dissertation will show, speculation enables a compiler writer to exploit dynamically occurring opportunities which would otherwise be difficult or even impossible to expose. Despite their potential, speculative optimizations typically involve complex implementation and significant compiler re-engineering. In comparison, the atomic region abstraction is both simple to incorporate into a compiler infrastructure and also exposes speculative opportunity to existing and unmodified optimizations. \n \nThe utility of the atomic region abstraction largely derives from its use of hardware atomicity---the execution of a region of code either completely, and as if all operations in the region occurred at one instant, or not at all. Hardware atomicity is an architectural primitive which provides software with a simple and intuitive model of execution, namely the ability to either explicitly commit or rollback a region of code. \n \nThe atomic region abstraction leverages hardware atomicity to enable a compiler writer to easily reason about and implement speculative optimization. In the atomic region abstraction, the compiler encapsulates commonly executed regions of the program using the hardware atomicity primitive. This permits the compiler to generate a speculative version of the code where uncommonly executed code paths are completely removed such that they do not need to be considered in (and hence do not constrain) a region's optimization. Pruned paths are converted into assert operations that trigger an abort in the uncommon case that one of these paths is needed. On an abort, hardware reverts state back to the beginning of the region and transfers control to a non-speculative version of the code. \n \nTwo implementations of the atomic region abstraction are also presented, the first of which demonstrates potential for a 10-15% average performance improvement in the context of a Java Virtual Machine, albeit running on simulated hardware. Incorporation of the atomic region abstraction is shown to be a simple and, thereby, a cost-effective means for exposing speculative optimization opportunities to the compiler. \n \nThe second implementation leverages a real system to demonstrate that at least some of these gains are achievable in practice. By incorporating the atomic region abstraction into the dynamic translator of the Transmeta Efficeon processor, practical concerns related to the identification of speculative opportunities and adaptation to misspeculations are explored. \nIn the context of this real system, a straightforward implementation using simple control \nmechanisms is shown to be sufficient to achieve a 3% average performance improvement.
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Craig Zilles, Naveen Neelakantam · 2011
This dissertation introduces the atomic region as a novel compiler abstraction which eases the development of speculative compiler optimizations. As this dissertation will show, speculation enables a compiler writer to exploit dynamically occurring opportunities which would otherwise be difficult or even impossible to expose. Despite their potential, speculative optimizations typically involve complex implementation and significant compiler re-engineering. In comparison, the atomic region abstraction is both simple to incorporate into a compiler infrastructure and also exposes speculative opportunity to existing and unmodified optimizations.
The utility of the atomic region abstraction largely derives from its use of hardware atomicity—the execution of a region of code either completely, and as if all operations in the region occurred at one instant, or not at all. Hardware atomicity is an architectural primitive which provides software with a simple and intuitive model of execution, namely the ability to either explicitly commit or rollback a region of code.
The atomic region abstraction leverages hardware atomicity to enable a compiler writer to easily reason about and implement speculative optimization. In the atomic region abstraction, the compiler encapsulates commonly executed regions of the program using the hardware atomicity primitive. This permits the compiler to generate a speculative version of the code where uncommonly executed code paths are completely removed such that they do not need to be considered in (and hence do not constrain) a region's optimization. Pruned paths are converted into assert operations that trigger an abort in the uncommon case that one of these paths is needed. On an abort, hardware reverts state back to the beginning of the region and transfers control to a non-speculative version of the code.
Two implementations of the atomic region abstraction are also presented, the first of which demonstrates potential for a 10–15% average performance improvement in the context of a Java Virtual Machine, albeit running on simulated hardware. Incorporation of the atomic region abstraction is shown to be a simple and, thereby, a cost-effective means for exposing speculative optimization opportunities to the compiler.
The second implementation leverages a real system to demonstrate that at least some of these gains are achievable in practice. By incorporating the atomic region abstraction into the dynamic translator of the Transmeta Efficeon processor, practical concerns related to the identification of speculative opportunities and adaptation to misspeculations are explored. In the context of this real system, a straightforward implementation using simple control mechanisms is shown to be sufficient to achieve a 3% average performance improvement.
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2008
In this paper, we introduce a new branch predictor that predicts the outcomes of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The design of a hybrid predictor comprising our branch predictor and a correlating branch predictor is presented. We also propose a new selector that chooses the most reliable prediction for each branch. This selector is based on the path followed to reach the branch. Results for immediate updates show a significant improvement with respect to a conventional hybrid predictor for different size configurations. In addition, the proposed hybrid predictor with a size of 8 KB achieves the same miss ratio as a conventional one of 64 KB. Performance evaluation for a dynamically-scheduled superscalar processor, with realistic updates, shows a speed-up of 11 % despite its higher latency (up to 4 cycles).
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Toshinori Sato · 2005
Recently there are many studies of data value prediction for increasing instruction level parallelism, and it is found that data speculation affects branch prediction accuracy. Even when data dependences are speculated successfully, processor performance would be degraded if branch prediction accuracy were decreased. On the other hand, branch prediction studies are nearly matured. While it becomes very difficult to increase the accuracy, there is still a vast gap between actual and ideal processor performance. From these considerations, we investigate to combine control and data speculation. Here, we evaluate the correlation between control speculation and data speculation and then propose to predict branch outcomes using data value prediction. Keywords: instruction level parallelism, speculative execution, branch prediction, value prediction, speculative verification.
Cited by 3
Tubella Murgadas, Jordi, González Colás, Antonio María · RECERCAT (Consorci de Serveis Universitaris de Catalunya)
This paper presents a mechanism to dynamically detect the loops that are executed in a program. This technique detects the beginning and the termination of the iterations and executions of the loops without compiler/user intervention. We propose to apply this dynamic loop detection to the speculation of multiple threads of control dynamically obtained from a sequential program. Based an the highly predictable behavior of the loops, the history of the past executed loops is used to speculate the future instruction sequence. The overall objective is to dynamically obtain coarse grain parallelism (at the thread level) that can be exploited by a multithreaded architecture. We show that for a 4-context multithreaded processor the speculation mechanism provides around 2.6 concurrent threads in average.
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González González, José, González Colás, Antonio María · RECERCAT (Consorci de Serveis Universitaris de Catalunya)
In this paper, we introduce a new branch predictor that predicts the outcomes of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The design of a hybrid predictor comprising our branch predictor and a correlating branch predictor is presented. We also propose a new selector that chooses the most reliable prediction for each branch. This selector is based on the path followed to reach the branch. Results for immediate updates show a significant improvement with respect to a conventional hybrid predictor for different size configurations. In addition, the proposed hybrid predictor with a size of 8 KB achieves the same miss ratio as a conventional one of 64 KB. Performance evaluation for a dynamically-scheduled superscalar processor, with realistic updates, shows a speed-up of 11% despite its higher latency (up to 4 cycles)
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Steven T. Katz, Steven Bayme · Continuity and Change · 2012
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Juan L. Aragón, Jesús González, Antonio González · IEEE Transactions on Computers · 2006
Conventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, increasing front-end energy and issue queue utilization and, thus, wasting around 30 percent of the power dissipated by a processor. Furthermore, processor design trends lead to increasing clock frequencies by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. As next-generation high-performance processors become deeply pipelined, the amount of wasted energy due to misspeculated instructions will go up. The aim of this work is to reduce the energy consumption of misspeculated instructions. We propose selective throttling, which triggers different power-aware techniques (fetch throttling, decode throttling, or disabling the selection logic) depending on the branch prediction confidence level. Results show that combining fetch-bandwidth reduction along with select-logic disabling provides the best performance in terms of overall energy reduction and energy-delay product improvement (14 percent and 10 percent, respectively, for a processor with a 22-stage pipeline and 16 percent and 13 percent, respectively, for a processor with a 42-stage pipeline).
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Dirk Grunwald · Plenum series in computer science · 2002
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