Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.
About 10,000 papers for “data cache”
Kenneth K. Chan, Cyrus C. Hay, John R. Keller et al. · 2014
Design of the HP PA 7200 CPU The PA 7200 processor chip is specifically designed to give enhanced performance in a four-way multiprocessor system without additional interface circuits. It has a new data cache organization, a prefetching mechanism, and two integer ALUs for general integer superscalar execution.
Cited by 0
SpringerReference · 2011
Cited by 0
Donald Yeung, Yan Solihin · Chapman & Hall/CRC computer and information science series · 2005
Cited by 0
S. Ramaswamy, Jaswanth Sreeram, Sudhakar Yalamanchili et al. · ACM SIGARCH Computer Architecture News · 2005
Benefits of advances in processor technology have long been held hostage to the widening processor-memory gap. Off-chip memory access latency is one of the most critical parameters limiting system performance. Caches have been used as a way of alleviating this problem by reducing the average memory access latency. The memory bottleneck assumes greater significance for high performance computer architectures with high data throughput requirements such as network processors.This paper addresses the memory bottleneck with the goal of minimizing off-chip memory demand and average memory access latency by proposing the use of small application specific compiler-visible data trace caches. We focus on tree data structures which are responsible for a significant component of the memory traffic in several applications. We have observed that tree accesses create a simple to characterize trace of memory references and propose a data trace cache design to exploit the locality of reference in these data traces.Our study reveals that data trace caches can reduce the total number of misses from 7% to 53% for accesses to rooted tree data structures as compared to a conventional cache for a variety of applications for small cache sizes (256 - 1024 bytes). Such caches are in keeping with the philosophy of victim caches, stream buffers, and pre-fetch buffers in that relatively small investments in silicon can realize substantive reduction in off-chip memory bandwidth demand.
Cited by 3
Subramanian Ramaswamy, Jaswanth Sreeram, Sudhakar Yalamanchili et al. · 2005
Benefits of advances in processor technology have long been held hostage to the widening processor-memory gap.Off-chip memory access latency is one of the most critical parameters limiting system performance. Caches have been used as a way of alleviating this problem by reducing the average memory access latency. The memory bottleneck assumes greater significance for high performance computer architectures with high data throughput requirements such as network processors. This paper addresses the memory bottleneck with the goal of minimizing off-chip memory demand and average memory access latency by proposing the use of small application specific compiler-visible data trace caches. We focus on tree data structures which are responsible for a significant component of the memory traffic in several applications. We have observed that tree accesses create a simple to characterize trace of memory references and propose a data trace cache design to exploit the locality of reference in these data traces.
Cited by 0
Shah Imran Alam, Samar Wazir, Aqeel khalique et al. · International Journal of Computer Science and Engineering · 2017
Cited by 1Open access
Lars Arge, Gerth Stølting Brodal, Rolf Fagerberg · Chapman & Hall/CRC computer and information science series · 2004
Cited by 20
Brad Calder, Chandra Krintz, Simmi John et al. · ACM SIGOPS Operating Systems Review · 1998
As the gap between memory and processor speeds continues to widen, cache eficiency is an increasingly important component of processor performance. Compiler techniques have been used to improve instruction cache pet$ormance by mapping code with temporal locality to different cache blocks in the virtual address space eliminating cache conflicts. These code placement techniques can be applied directly to the problem of placing data for improved data cache pedormance.In this paper we present a general framework for Cache Conscious Data Placement. This is a compiler directed approach that creates an address placement for the stack (local variables), global variables, heap objects, and constants in order to reduce data cache misses. The placement of data objects is guided by a temporal relationship graph between objects generated via profiling. Our results show that profile driven data placement significantly reduces the data miss rate by 24% on average.
Cited by 9Open access
Živojin Šuštran, Goran Rakočević, Veljko Milutinović · Advances in computers · 2015
Cited by 4
Sung‐Eui Yoon, Enrico Gobbetti, David J. Kasik et al. · Synthesis lectures on computer graphics and animation · 2008
Cited by 0
Rolf Fagerberg, Gerth Stølting Brodal, Lars Arge · University of Southern Denmark Research Portal (University of Southern Denmark) · 2005
Cited by 0
J. Lee · 2007
No abstract available.
Cited by 0
Science · 2003
Climate scientists probing the soil's role in carbon cycling and hydrologists studying river flow will find plenty of useful information in this archive of ecological and geochemical data sets from Oak Ridge National Laboratory in Tennessee. The nearly 700 databases hold measurements recorded by satellites and earthbound scientists, as well as results of computer modeling. Many center around efforts to understand carbon storage in ecosystems, a matter of great interest because plants help soak up humanmade carbon dioxide that would otherwise contribute to global warming.
Cited by 0
Brad Calder, Chandra Krintz, Simmi John et al. · 1998
As the gap between memory and processor speeds continues to widen, cache eficiency is an increasingly important component of processor performance. Compiler techniques have been used to improve instruction cache pet$ormance by mapping code with temporal locality to different cache blocks in the virtual address space eliminating cache conflicts. These code placement techniques can be applied directly to the problem of placing data for improved data cache pedormance.In this paper we present a general framework for Cache Conscious Data Placement. This is a compiler directed approach that creates an address placement for the stack (local variables), global variables, heap objects, and constants in order to reduce data cache misses. The placement of data objects is guided by a temporal relationship graph between objects generated via profiling. Our results show that profile driven data placement significantly reduces the data miss rate by 24% on average.
Cited by 266Open access
????????? · The Royal Society of Chemistry’s Journals, Books and Databases (The Royal Society of Chemistry) · 2013
Cited by 0
Wei Zhang · IEEE Transactions on Computers · 2005
Soft error conscious cache design has become increasingly crucial for reliable computing. The widely used ECC or parity-based integrity checking techniques have only limited capability in error detection and correction, while incurring nontrivial penalty in area or performance. The N modular redundancy (NMR) scheme is too costly for processors with stringent cost constraints. This paper proposes a cost-effective solution to enhance data reliability significantly with minimum impact on performance. The idea is to add a small fully associative cache to store the replica of every write to the L1 data cache. Due to data locality and its full associativity, the replication cache can be kept small while providing replicas for a significant fraction of read hits in L1, which can be used to enhance data integrity against soft errors. Our experiments show that a replication cache with eight blocks can provide replicas for 97.3 percent of read hits in L1 on average. Moreover, compared with the recently proposed in-cache replication schemes, the replication cache is more energy efficient, while improving the data integrity against soft errors significantly.
Cited by 65
Wei Zhang, Sudhanva Gurumurthi, Mahmut Kandemir et al. · 2004
Processor caches already play a critical role in the performance of today’s computer systems. At the same time, the data integrity of words coming out of the caches can have serious consequences on the ability of a program to execute correctly, or even to proceed. The integrity checks need to be performed in a time-sensitive manner to not slow down the execution when there are no errors as in the common case, and should not excessively increase the power budget of the caches which is already high. ECC and parity-based protection techniques in use today fall at either extremes in terms of compromising one criteria for another, i.e., reliability for performance or vice-versa. This paper proposes a novel solution to this problem by allowing in-cache replication, wherein reliability can be enhanced without excessively slowing down cache accesses or requiring significant area cost increases. The mechanism is fairly power efficient in comparison to other alternatives as well. In particular, the solution replicates data that is in active use within the cache itself while evicting those that may not be needed in the near future. Our experiments show that a large fraction of the data read from the cache have replicas available with this optimization.
Cited by 124
Low Power · 2008
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (transistor threshold voltage) process. We utilize the concept of Gated-Ground [5] (NMOS transistor inserted between Ground line and SRAM cell) to achieve reduction in leakage energy without significantly affecting performance. Experimental results on gated-Ground caches show that data is retained (DRG-Cache) even if the memory are put in the stand-by mode of operation. Data is restored when the gated-Ground transistor is turned on. Turning off the gated-Ground transistor in turn gives large reduction in leakage power. This technique requires no extra circuitry; row decoder itself can be used to control the gated-Ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25µ technology to show the data retention capability and the cell stability of DRG-cache. Our simulation results on 100nm and 70nm processes (Berkeley Predictive Technology Model) show 16.5 % and 27 % reduction in consumed energy in L1 cache and 50 % and 47 % reduction in L2 cache with less than 5 % impact on execution time and within 4 % increase in area overhead.
Cited by 0
Jiao Feng · 2004
Through the analysis and research of the current data cache technology, a distributed data cache system based on cache-network in this paper is proposed so as to improve the performance of data cache system and the retrieve efficiency of the client/server networks by reducing transmission time and balancing load. The main point of the data cache system is to set up data cache section in each node of network and to realize unified allocation and management of the cache sections. Through analyzing the performance of the cache system and the comparison with other cache systems, the results show the efficiency of the cache system.
Cited by 0
Afrin Naz · 2007
Existing cache organization suffers from the inability to distinguish different types of localities, and non-selectively cache all data rather than making any attempt to take special advantage of the locality type. This causes unnecessary movement of data among the levels of the memory hierarchy and increases in miss ratio. In this dissertation I propose a split data cache architecture that will group memory accesses as scalar or array references according to their inherent locality and will subsequently map each group to a dedicated cache partition. In this system, because scalar and array references will no longer negatively affect each other, cache-interference is diminished, delivering better performance. Further improvement is achieved by the introduction of victim cache, prefetching, data flattening and reconfigurability to tune the array and scalar caches for specific application. The most significant contribution of my work is the introduction of novel cache architecture for embedded microprocessor platforms. My proposed cache architecture uses reconfigurability coupled with split data caches to reduce area and power consumed by cache memories while retaining performance gains. My results show excellent reductions in both memory size and memory access times, translating into reduced power consumption. Since there was a huge reduction in miss rates at L-1 caches, further power reduction is achieved by partially or completely shutting down L-2 data or L-2 instruction caches. The saving in cache sizes resulting from these designs can be used for other processor activities including instruction and data prefetching, branch-prediction buffers. The potential benefits of such techniques for embedded applications have been evaluated in my work. I also explore how my cache organization performs for non-numeric data structures. I propose a novel idea called "Data flattening" which is a profile based memory allocation technique to compress sparsely scattered pointer data into regular contiguous memory locations and explore the potentials of my proposed Spit cache organization for data treated with data flattening method.
Cited by 0Open access