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About 680 papers for “delay fault testing”
Niraj K. Jha, Sandeep K. Gupta · Cambridge University Press eBooks · 2003
Delay fault testing exposes temporal defects in an integrated circuit. Even when a circuit performs its logic operations correctly, it may be too slow to propagate signals through certain paths or gates. In such cases, incorrect logic values may get latched at the circuit outputs.
Cited by 11
Erik Chmelar Center · 2007
Interconnection networks consume the majority of the die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple delay and/or bridging interconnection faults. This method achieves an adjustable, maximum sensitivity to resistive open defects of several kilo-ohms. Bridging faults modeled as either wired-AND or wired-OR are detectable. Finally, fast and simple fault localization is presented. 1
Cited by 0
E. Chmelaf · 2004
Interconnection networks consume the majority of the die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple delay and/or bridging interconnection faults. This method achieves an adjustable, maximum sensitivity to resistive open defects of several kilo-ohms. Bridging faults modeled as either wired-AND or wired-OR are detectable. Finally, fast and simple fault localization is presented.
Cited by 51
Angela Krstić, Kwang‐Ting Cheng · Frontiers in electronic testing · 1998
Cited by 308
2008
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple interconnect delay faults, multiple bridging faults, or both. An adjustable maximum sensitivity to resistive open defects of several kilo-ohms is achieved. A bridging fault that causes a signal transition to occur on at least one of the bridged interconnects is detectable. Finally, fast and simple fault location is presented. 1
Cited by 0
Yuejian Wu, P. Soong · 1999
In high speed systems, the AC performance of interconnects on boards and backplanes are critical. Today, most companies rely on functional test vectors to conduct interconnect delay fault tests. Besides poor fault coverage, this approach does not provide much diagnostic information when faults are detected. Based on the concept of early capture and late update, this paper proposes a novel technique to conduct board interconnect delay fault test using a IEEE 1149.1 standard TAP controller. The proposed technique does not require any extra pin to ASICs, does not require any modification of standard boundary scan cells and uses a standard TAP controller. The costs of the proposed technique include only a few flip-flops plus some gates in a TAP controller wrapper without modification of the standard TAP controller itself.
Cited by 4
Bin Li, Lei Fang, Michael S. Hsiao · 2007
In today's deep sub-micron designs, large amounts of switching activity may cause a substantial voltage drop on the power rails, also called power droop. Faults that may result from a power droop include delay faults caused by the increased propagation delays from the reduced supply voltage. In order to assess the performance of a manufactured chip, its worst-case droop condition should be tested by applying a specific input pattern which can cause maximum switching activity. On the contrary, during delay fault diagnosis, it would be beneficial for the diagnostic patterns to induce less switching activity in order to filter the embedded noise. In this paper, we propose a new SAT formulation that incorporates depth-limited search to compute the test patterns for these power droop faults. Experimental results demonstrate the efficiency of the proposed approach for generating test patterns for both transition and path-delay faults that also produce maximal (or minimal) power. Up to three orders of magnitude speed-up can be achieved using our approach.
Cited by 11
E.S. Park, M.R. Mercer, T.W. Williams · IEEE Design & Test of Computers · 1989
The authors propose a statistical model for measuring delay-fault coverage. The model provides a figure of merit for delay testing in the same way that fault coverage provides one for the testing of single stuck-at faults. The mode measures test effectiveness in terms of the propagation delay of the path to be tested, the size of the delay defect, and the system clock interval, and then combines the data for all delay faults to measure total delay-fault coverage. The authors also propose a model for measuring the defect level as a function of the manufacturing yield and the predictions of the statistical delay-fault coverage model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 39
Jaeyong Chung, Jacob A. Abraham · 2009
This paper presents a new path selection algorithm for delay fault testing in a statistical timing framework. Existing algorithms which consider correlation between paths use an iterative process for each path or defect and require a Monte Carlo simulation for each iteration to calculate the conditional fault probability. The proposed algorithm does not require the iteration process and selects a requested number of paths simultaneously once it performs a statistical timing analysis at the beginning. If selection of k paths is required in a set of paths, it partitions the set into two path sets and determines how many paths should be selected in each path set out of the k paths. It recursively continues this process and ends up with k paths. The partitioning is easily performed during the recursive traversal of a circuit, which produces an imaginary path tree, where paths are already grouped based on their prefix. Experimental results show the proposed algorithm can effectively use structural correlation and spatial correlation to generate high quality path sets.
Cited by 9
M. Abramovici, Charles E. Stroud · Journal of Electronic Testing · 2003
Cited by 38
M. Abramovici, Charles E. Stroud · 2003
We present the first delay-fault testing approach for FPGAs, applicable both for manufacturing and for on-line testing. Our approach is based on BIST, is comprehensive, and does not require expensive ATE. We have successfully implemented this BIST approach on the ORCA 2C series FPGA.
Cited by 47
Spyros Tragoudas, Nathan Denny · ACM Transactions on Design Automation of Electronic Systems · 2003
Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of path delay faults that need to be tested in a circuit. In order to have a minimal impact on the operation clock and more accuracy in testing, it is proposed that test points should be inserted with the additional constraint that every path has a bounded number of test points. A polynomial time solvable integer linear programming (ILP) formulation serves as the basis for the presented test placement methodology. Due to the ILP's global optimization property we achieve results that are comparable to those by an existing greedy technique for the less constrained test point placement problem.
Cited by 2
N. B. Zain Ali, Mark Zwoliński, Bashir M. Al‐Hashimi et al. · 2006
The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover.
Cited by 36
Bart Vermeulen, Sybille Hellebrand · 2010
Cited by 0
Brian T. Cunningham, W.K. Fuchs, Prithviraj Banerjee · 1987
Cited by 4
Pierzynska, Alicja · Summit (Simon Fraser University) · 1997
Cited by 1Open access
Joonyoung Kim, Jesse Whittemore, João Marques‐Silva et al. · 2000
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has been typically applied to EDA as follows: (1) formulation of the given problem as a SAT instance (2) solution of the SAT instance. In this paper we present a method to simultaneously solve several closely related SAT instances using incremental satisfiability (ISAT). In ISAT, the decision sequence made for a function is used to solve another set of functions which have a number of new constraints (extensions) added to the prefix function. Our experiments show that we can achieve significant gains in total runtime when we use this methodology as opposed to resetting the decision sequences and solving each instance from scratch. Application of ISAT to delay fault testing is presented by formulating incremental path sensitization as an ISAT problem. Non-robust tests for the combinational portion of ISCAS 89 circuits are generated using this method.
Cited by 29
Singh, Inoue, Saluja et al. · 2003
This paper presents a software-based self-testing methodology for delay fault testing. Delay faults affect the circuit functionality only when it can be activated in functional mode. A systematic approach or the generation of test vectors, which are applicable in functional mode, is presented. A graph theoretic model (represented by IE-Graph) is developed in order to model the datapath. A finite state machine model is used for the controller. These models are used for constraint extraction so that the generated test can be applied in functional mode.
Cited by 11
H.T. Vergos, Yiorgos Tsiatouhas, Th. Haniotakis et al. · International Journal of Electronics · 2001
In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are not single path propagating hazard free robustly testable (SPP-HFRT) and we present a path selection method such that all the selected paths are SPP-HFRT by (O log2 n) test-vector pairs, where n is the length of the shifter’s operand. The propagation delay along all other paths is a function of the delays along the selected paths. This is the ® rst work addressing the problem of shifter path delay fault testing. 1.
Cited by 0
Joonyoung Kim, J. Whittemore, J.P. Marques-Silva et al. · Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) · 2002
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has been typically applied to EDA as follows: (1) formulation of the given problem as a SAT instance (2) solution of the SAT instance. In this paper we present a method to simultaneously solve several closely related SAT instances using incremental satisfiability (ISAT). In ISAT, the decision sequence made for a "prefix" function is used to solve another set of functions which have a number of new constraints (extensions) added to the prefix function. Our experiments show that we can achieve significant gains in total runtime when we use this methodology as opposed to resetting the decision sequences and solving each instance from scratch. Application of ISAT to delay fault testing is presented by formulating incremental path sensitization as an ISAT problem. Non-robust tests for the combinational portion of ISCAS 89 circuits are generated using this method.
Cited by 2