Heba Shawkey, Dalia A. El-Dib, Z. Abid · International Journal of Electronics · 2010
An aggressive drowsy cache block management, where the cache block is forced into drowsy mode all the time except during write and read operations, is proposed. The word line (WL) is used to enable the normal supply voltage (V DD_high) to the cache line only when it is accessed for read or write whereas the drowsy supply voltage (V DD_low) is enabled to the cache cell otherwise. The proposed block management neither needs extra cycles nor extra control signals to wake the drowsy cache cell, thereby reducing the performance penalty associated with traditional drowsy caches. In fact, the proposed aggressive drowsy mode can reduce the total power consumption of the traditional drowsy mode by 13% or even more, depending on the cache access rate, access frequency and the CMOS technology used.
Cited by 2
Major Bhadauria, Sally A. Mckee, Karan Singh et al. · 2008
Minimizing power consumption continues to grow as a critical design issue for many platforms, from embedded systems to CMPs to ultrascale parallel systems. As growing cache sizes consume larger portions of the die, leakage current becomes an increasingly important component in overall power. Since most cache lines remain idle most of the time, drowsy caching techniques that reduce voltages on selected lines can reduce this leakage power. Most drowsy caching policies in the literature update drowsy/non-drowsy state after a given execution window: e.g., the widely used simple policy puts all caches lines to sleep after a specified number of clock cycles. Such methods are inherently architecturespecific. We instead introduce a drowsy caching mechanism
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Rodrigo M. Sokulski, Emmanuell D. Carreño, Marco A. Z. Alves · 2018
In the last decades, with the continuous increase in the number of transistors on the same chip, a bigger die area inside the processor have been occupied by the cache memories, in some cases, the caches occupy close to half of the chip area in modern processors. For this reason, more energy is consumed by this dedicated circuit, making energy saving techniques for cache memories an important subject. In this paper, we evaluate the integration of a state-of-the-art dead cache line predictor with the Drowsy technique in the last level cache.
Cited by 2
Turk J Elec Eng, Comp Sci, Sunghoon Shim et al. · 2015
consumption. The drowsy cache technique is known as one of the most popular techniques for reducing the leakage power consumption in the data cache. However, the drowsy cache is reported to degrade the processor performance signi cantly. In this paper, to maintain the performance of the processor with the drowsy cache technique, we propose an early wakeup technique, which predicts the next cache line to be requested by utilizing the way-prediction information. The proposed technique eciently reduces the number of accesses to the cache lines in drowsy mode. Our simulation results show that the proposed technique reduces the extra delay due to the drowsy cache scheme by 29.6%, on average.
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Bramha Allu, Wei Zhang · 2004
As feature sizes shrink, leakage energy reduction has become increasingly important, especially for cache memories. Recent research in drowsy instruction cache shows that the leakage energy of the instruction cache can be significantly reduced with little performance degradation by exploiting the instruction spatial locality at the cache sub-bank level[5]. The performance penalty due to the sub-bank wake-up latency is dramatically reduced by using a prediction buffer to pre-activate the next sub-bank at runtime. However, consulting the prediction buffer at every cache access consumes non-trivial dynamical energy, which can compromise the overall energy savings substantially. This paper proposes a static approach to capture the sub-bank transition behavior at link time and to pre-activate the instruction cache sub-bank at runtime according to the compiler-directed hints. We also propose a hybrid approach to exploit both the static and dynamic information for reducing the performance penalty further with little dynamic energy overhead. Our experiments reveal that the static approach is very successful in capturing the sub-bank transition behavior for reducing the performance penalty and it also reduces 38.2% more leakage energy than the hardware-based approach, taking the dynamic energy overhead into account. Moreover, our results show that the hybrid approach is the best strategy for the drowsy instruction cache to balance leakage energy reduction and performance.
Cited by 7
Wei Li, Jianqing Xiao · Lecture notes in electrical engineering · 2013
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Debasis Mukherjee, B.V. Ramana Reddy · Advanced materials research · 2011
Leakage Current is found to be gradually increasing in CMOS VLSI circuits with advance of technologies, specially in nanometer range. Though area of a transistor is becoming less and lesser, but precious control over the operations of a transistor is not possible in such a small structure. Reductions of threshold voltage, channel length, and gate oxide thickness are responsible for generation of leakage current. In this paper we have reviewed eight types of leakage current present in CMOS VLSI circuits, namely 1. Reverse Bias pn Junction Current, 2. Sub-threshold Leakage, 3. Drain Induced Barrier Lowering Effect, 4. Gate Induced Drain Leakage current, 5. Punch Through, 6. Narrow Channel Effects, 7. Gate Oxide Tunneling leakage current and 8. Hot-Carrier Injection. After that, we have reviewed 6-T SRAM read and write operation. Next to that, we have reviewed three techniques of leakage reduction namely 1. Transistor Stacking Effect, 2. Data Retention Gated-Ground Cache and 3. Drowsy Cache. We have reproduced the simulation result of these leakage minimization techniques. Finally we have shown comparison of 1. Conventional 6-T SRAM leakage current, 2. leakage current using Data Retention Gated-Ground Cache techniques and 3. leakage current using Drowsy Cache techniques. To obtain these three results we have used Cadence Virtuso & SoC Encounter tools. All these three results has been simulated with IBM 90 nanometer technology file.
Cited by 3
N N V Sai Prakash, Israel Koren, C.M. Krishna · Journal of Low Power Electronics · 2013
Energy consumption and speed of execution have long been recognized as conflicting requirements for processor design. In this work, we have developed a low-cost dynamic architecture adaptation scheme to save leakage power in caches. This design uses voltage scaling to implement drowsy caches. The importance of a dynamic scheme for managing drowsy caches, arises from the fact that not only does cache behavior change from one application to the next, but also during different phases of execution within the same application. We discuss various implementations of our scheme that provide a tradeoff between granularity of control and design complexity.\nWe investigate a combination of policies where the cache lines can be turned off completely if they are not accessed, when in the drowsy mode. We also develop a simple dynamic cache-way shutdown mechanism, and propose a combination of our dynamic scheme for drowsy lines, with the cache-way shutdown scheme. Switching off cache ways has the potential of greater energy benefits but provides a very coarse grained control. Combining this with the fine grained scheme of drowsy cache lines allows us to exploit more possibilities for energy benefits without incurring a significant degradation in performance.\nKeywords: Drowsy Cache, Architecture Adaptation, Low Power, Leakage Reduction, Dynamic Scheme
Cited by 0Open access
Prakash, Nitin · Scholarworks (University of Massachusetts Amherst) · 2012
Energy consumption and speed of execution have long been recognized as conflicting requirements for processor design. In this work, we have developed a low-cost dynamic architecture adaptation scheme to save leakage power in caches. This design uses voltage scaling to implement drowsy caches. The importance of a dynamic scheme for managing drowsy caches, arises from the fact that not only does cache behavior change from one application to the next, but also during different phases of execution within the same application. We discuss various implementations of our scheme that provide a tradeoff between granularity of control and design complexity. We investigate a combination of policies where the cache lines can be turned off completely if they are not accessed, when in the drowsy mode. We also develop a simple dynamic cache-way shutdown mechanism, and propose a combination of our dynamic scheme for drowsy lines, with the cache-way shutdown scheme. Switching off cache ways has the potential of greater energy benefits but provides a very coarse grained control. Combining this with the fine grained scheme of drowsy cache lines allows us to exploit more possibilities for energy benefits without incurring a significant degradation in performance. Keywords: Drowsy Cache, Architecture Adaptation, Low Power, Leakage Reduction, Dynamic Scheme
Cited by 0
Daniele Rossi, Vasileios Tenentes, S.M. Reddy et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2017
In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in subthreshold current due to BTI aging. We develop a simulation framework to evaluate tradeoffs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.
Cited by 15Open access
Saghir, Ahsan · Knowledge Commons (Lakehead University) · 2016
In this thesis, we propose two optimization techniques to reduce power consumption in L1 caches (data, texture and constant), shared memory and L2 cache. The first optimization technique targets static power. Evaluation of GPGPU applications shows that once a cache block is accessed by a thread, it takes several hundreds of clock cycles until the same block is accessed again. The long inter-access cycle can be used to put cache cells into drowsy mode and reduce static power. While drowsy cells reduce static power, they increase access time as voltage of a cache cell in drowsy mode should be raised before the block can be accessed. To mitigate performance impact of drowsy cells, we propose a novel technique called coarse grained drowsy mode. In coarse grained drowsy mode, we partition each cache into regions of consecutive cache blocks and wake up a region upon cache access. Due to temporal and spatial locality of cache accesses, this method dramatically reduces performance impact caused by drowsy cells. The second optimization technique relies on branch divergence in GPGPUs. The execution model in GPGPUs is Single Instruction Multiple Thread (SIMT) which means processing cores execute the same instruction with different data for GPGPU threads. The SIMT execution model may result in divergence of threads when a control instruction is executed. GPGPUs execute branch instructions in two phases. In the first phase, threads in the taken path are active and the rest are idle. In the second phase, threads in the not-taken path are executed and the rest are idle. Contemporary GPGPUs access all portions of cache blocks, although some threads are idle due to branch divergence. We propose accessing only portions of cache blocks corresponding to active threads. By disabling unnecessary sections of cache blocks, we are able to reduce dynamic power of caches. Our results show that on average, the two optimization techniques together reduce power of caches by up to 98% and 15% for static and dynamic power, respectively.
Cited by 0Open access
Nam Sung Kim, Krisztián Flautner, David Blaauw et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. As feature sizes shrink, the dominant component of this power consumption will be leakage. However, during a fixed period of time, the activity in a data cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large data caches by putting the cold cache lines into a state preserving, low-power drowsey mode. In this paper, we investigate policies and circuit techniques for implementing drowsy data caches. We show that with simple microarchitectural techniques, about 80%-90% of the data cache lines can be maintained in a drowsy state without affecting performance by more than 0.6%, even though moving lines into and out of a drowsy state incurs a slight performance loss. According to our projections, in a 70-nm complementary metal-oxide-semiconductor process, drowsy data caches will be able to reduce the total leakage energy consumed in the caches by 60%-75%. In addition, we extend the drowsy cache concept to reduce leakage power of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. In order to enable drowsy instruction caches, we propose a technique called cache subbank prediction, which is used to selectively wake up only the necessary parts of the instruction cache, while allowing most of the cache to stay in a low-leakage drowsy mode. This prediction technique reduces the negative performance impact by 78% compared with the no-prediction policy. Our technique works well even with small predictor sizes and enables a 75% reduction of leakage energy in a 32-kB instruction cache.
Cited by 110
Wei Pei, Wen-Ben Jone, Yiming Hu · 2007
Due to the spatial-locality property of data caches and the temporal-locality property of instruction caches, signif- icant leakage reduction can be achieved by switching a large number of cache lines into the low-power standby or drowsy mode. It has been shown that 80%-90% of the data cache lines can be maintained in drowsy state without affecting the performance by more than 0.6% (IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 167-184, Feb. 2004). However, with the introduction of the drowsy-cache design technique, new fault be- haviors appear and more restrictive design rules must be applied to the chip fabrication process. In this paper, we simulate all possible spot defects (SDs) under normal mode and drowsy mode in different resistance regions using HSpice. Six new fault models appear with the introduction of drowsy mode for memory arrays. When we derive a march algorithm for the new fault models of this low-power cache, several simplification rules are utilized to reduce the test complexity. According to these simplification rules, each of these new faults has its equivalent counterpart existent in both data caches and instruction caches. As a result, we develop a march algorithm which can detect all SDs in either data caches or instruction caches. Since some faults occur only in drowsy mode, a built-in self-repair (BISR) scheme is developed. By utilizing BISR, the cache can still work even if some cache lines fail to work in drowsy mode.
Cited by 0
Nam Sung Kim, K. Flautner, D. Blaauw et al. · 2003
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. In our previous work we have shown how the drowsy circuit - a simple, state-preserving, low-leakage circuit that relies on voltage scaling for leakage reduction - can be used to reduce the total energy consumption of data caches by more than 50%. In this paper, we extend the architectural control mechanism of the drowsy cache to reduce leakage power consumption of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. To enable drowsy instruction caches, we propose a technique called cache sub-bank prediction which is used to selectively wake up only the necessary parts of the instruction cache, while allowing most of the cache to stay in a low leakage drowsy mode. This prediction technique reduces the negative performance impact by 76% compared to the no-prediction policy. Our technique works well even with small predictor sizes and enables an 86% reduction of leakage energy in a 64 K byte instruction cache.
Cited by 38
Dharmesh Parikhz, Yan Zhangy, Karthik Sankaranarayananz et al. · 2009
Abstract This paper compares the effectiveness of state-preserving andnon-state-preserving techniques for leakage control in caches by comparing drowsy cache and gated-Vss for data caches using70nm technology parameters. To perform the comparison, we use "HotLeakage", a new architectural model for subthreshold andgate leakage that explicitly models the effects of temperature, voltage, and parameter variations, and has the ability to recalculateleakage currents dynamically as temperature and voltage change at runtime due to operating conditions, DVS techniques, etc.By comparing drowsy-cache and gated-V ss at different L2 la-tencies, we are able to identify a range of operating parameters at which gated-Vss is more energy efficient than drowsy-cache, eventhough gated-V ss does not preserve data in cache lines that havebeen deactivated. We are also able to show potential further benefits of gated-Vss if an effective dynamic adaptation technique canbe found.
Cited by 0
Mrinmoy Ghosh, et al. · 2008
This paper proposes Virtual Exclusion, an architectural technique to reduce leakage energy in the L2 caches for cache-coherent multiprocessor systems. This technique leverages two previously proposed circuits techniques — gated Vdd and drowsy cache, and proposes a low cost, easily implementable scheme for cache-coherent multiprocessor systems. The Virtual Exclusion scheme saves leakage energy by keeping the data portion of repetitive cache lines off in the large higher level caches while still manages to maintain Multi-Level Inclusion, an essential property for an efficient implementation of conventional cache coherence protocols. By exploiting the existing state information in the snoop-based cache coherence protocol, there is almost no extra hardware overhead associated with our scheme. In our experiments, the SPLASH-2 multiprocessor benchmark suite was correctly executed under the new Virtual Exclusion policy and showed an up to 72 % savings of leakage energy (46 % for SMP and 35 % for multicore in L2 on average) over a baseline drowsy L2 cache.
Cited by 0
Nam Sung Kim, Trevor Mudge · Deep Blue (University of Michigan) · 2004
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature sizes shrink and threshold voltages decrease, sub-threshold leakage is becoming the dominant component of this power consumption. In this study we examine various circuit and microarchitectural techniques for low-leakage on-chip caches, designed with nano-scale complementary-metal-oxide semiconductor (CMOS) technologies. First, a low-leakage circuit technique using dynamic voltage scaling for static random access memory (SRAM) is proposed. It is based on an SRAM cell that can be placed in a low power drowsy state. In a projected 70nm technology, the drowsy state reduces memory cell leakage power by 96% and has a fast wake-up to the active state of one or two cycles. Second, microarchitectural techniques for controlling L1 data caches are presented. They cut the leakage power of large data caches by putting the cold cache lines into a drowsy mode. The drowsy data cache is able to reduce the leakage energy by 75% without affecting performance by more than 0.6%. Third, the drowsy cache concept is extended to reduce the leakage power of instruction caches. Our results show that data and instruction caches require different control strategies to be effective. Furthermore, to reduce the bit-line leakage through the access transistors in drowsy caches, a predictive gated precharge is proposed. The combination of these two techniques reduces the leakage power by 72% with negligible (0.3%) run-time increase. Finally, we show that larger than normal slow L2 caches with high V<sub> TH</sub>'s, or smaller than normal leaky (low V<sub>TH</sub>) L1 caches result in lower power two level cache systems, that leave the average access time unchanged: size can be traded for power in an unintuitive fashion. In summary, this study focuses on microprocessor on-chip caches designed with future technologies. We show that to effectively control leakage power with a minimum processor performance impact, it is necessary to consider both the circuit and microarchitecture simultaneously.
Cited by 0
Michael J. Geiger, Sally A. McKee, Gary Tyson · 2005
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal partitioning reduces average power per data access by employing multiple smaller structures or using cache subbanks. For instance, region-based caching places small caches dedicated to stack and global accesses next to the L1 data cache. With respect to static power dissipation, leakage power may be addressed at both circuit and architectural levels. Drowsy caches reduce leakage power by keeping inactive lines in a low-power mode. Here we merge drowsy and region-based caching to reduce overall cache power consumption, showing that the combination yields more benefits than either alone. Applications from the MiBench suite exhibit power reductions in the cache system of up to 68-71%, depending on memory configuration, with a small increase in execution time
Cited by 17
Massimo Alioto, P. Bennati, Roberto Giorgi · 2010
In this paper, a technique to reduce the leakage power consumption in embedded drowsy instruction caches (I caches) is proposed. The technique is called “Improved Drowsy” (ID), and adopts a more efficient strategy than standard Drowsy Caches (DCs) to turn off unused cache lines, based on locality. The implementation of ID caches requires minor changes, and the area/speed overhead associated with the additional circuitry is insignificant. The proposed technique is assessed through circuit and cycle accurate simulations on an L1 instruction cache embedded in an ARM XScale processor based system in a 65 nm CMOS technology. Results show that this technique is able to reduce the leakage power by 69% on average. Leakage of DC is shown to be significantly lowered with the proposed ID approach, being DC leakage greater than that of ID by up to 53%, and 10 15% typically.
Cited by 6
Michael J. Geiger · 2005
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal partitioning reduces average power per data access by employing multiple smaller structures or using cache subbanks. For instance, region-based caching places small caches dedicated to stack and global accesses next to the L1 data cache. With respect to static power dissipation, leakage power may be addressed at both circuit and architectural levels. Drowsy caches reduce leakage power by keeping inactive lines in a low-power mode. Here we merge drowsy and region-based caching to reduce overall cache power consumption, showing that the combination yields more benefits than either alone. Applications from the MiBench suite exhibit power reductions in the cache system of up to 68-71%, depending on memory configuration, with a small increase in execution time.
Cited by 0