O.-c. Mourad, S.-M. Lotfy, Mohamad Noureddine et al. · 2007
The paper presents a parallel reconfigurable hardware implementation of the AES cryptographic algorithm developed for an embedded application. This new methodology directly maps a design described in a high level language, Handel-C, to FPGA platforms. The Handel-C approach narrows the gap between performance and flexibility, and thus, reduce the risk of translating a high level prototype into HDLs. It provides a high degree of flexibility from two viewpoints: the language level of abstraction and the hardware reconfiguration. Using Handel-C, we enhanced the performance of the designed unit by applying parallelism and reconfigurability. Our FPGA implementations show that superior performance can be achieved compared with software and hardware implementations counterparts. In particular, our design outperforms most of the other designs in speed. At the same time, the area cost for putting the AES algorithm on the same hardware core is also kept as low as possible.
Cited by 17
2010
Abstract. With the security of standardised cryptographic hash functions in question, interest in new designs based on provably secure foundations has been reignited. LASH is a hash function design whose security is related to hard lattice problems. Although the tightness of the security reduction is dubious, LASH makes an interesting trade-off in that it is claimed to offer efficient implementations in comparison to alternatives such as VSH. In this paper we investigate this claim by investigating implementations of LASH in software and hardware, and by examining the issue of physical security; all of these aspects are crucial to the deployment of LASH in an embedded environment. 1
Cited by 0
Bojan Pikl · 2011
The goal of this thesis is to describe a production of an embedded computer. The thesis describes development and production of an embedded computer for the medical diode laser DL30 that is being developed in Robomed d.o.o.. The first part of the thesis describes the choice of hardware devices. I mostly describe the technologies that one can buy on the market. Moreover for every part of the computer installed and developed there is an argument why we selected that exact part. The second part of the thesis describes how to make and deploy an image of the Windows Embedded CE 6.0R3 operating system. Later we find how to connect target computer to the development computer. At the end one can find the development of a few parts of the dedicated application written in Silverlight for Windows Embedded.
Cited by 0
Markus Kögel, Pablo Zometa, Rolf Findeisen · MPG.PuRe (Max Planck Society) · 2012
Cited by 0
K. Jayashree, S. Prasanna Babu · International Journal of Computer Applications · 2014
The main objective of Research is to implement embedded agile methodology using microcontroller. In earlier years agile methods have seen , individually , earn a worldwide following. The agile methods are used to indicate an advance in good practices of software development life cycle , but the advantages of agile methods changes across the different regions of software development. Embedded systems is an best illustration of a software development regime in which implementation of agile methods can be challenging, and the pros of using agile methods may not be as marked as in other systems of software development. This paper explains how the different aspects of embedded software development affect the usage of agile methods to field of embedded. Developers ,stakeholder,business and end user should see developed schedule performance and product quality. Developers should get capablity of regular feedback of iteractive development Tdd and spend a lot less time finding errors. Stakeholder, Business should see imporved certain and visible fact based of management data .Even though the whole result of using agile methods in embedded system software development is an improving efficiency , cautious method is needed to get the potential benefits.
Cited by 0Open access
Wu, Haotian · DR-NTU (Nanyang Technological University) · 2025
With the rapid development of AI (Artificial Intelligence) technology, its application and deployment on embedded platforms has become one of the key research focuses in the industry. YOLO (You Only Look Once) is the most frequently mentioned algorithm. However, traditional CPU (Central Processing Unit) unable to meet the real-time requirements. The power consumption of high-performance GPU (Graphics Processing Unit) is not acceptable for end devices. FPGAs (Field-Programmable Gate Arrays) achieve efficient computation and memory access, made them the mainstream choice for embedded deployment. Vitis HLS (High-Level Synthesis) enables the conversion from high-level to hardware languages, greatly simplifying the development process. This dissertation takes the lightweight but highly accurate YOLOv4-tiny model as the research object and realizes efficient acceleration on the Xilinx ZYNQ-7020 platform through overlapping architectures reusable PE (Processing Element) design, as well as various optimization strategies such as ping-pong buffering, operator fusion, data reuse and quantization mechanism with HLS primitive instructions. Through hardware and software co-design and integration, we achieved a frame rate of 15.58 FPS (Frames Per Second) at a clock frequency of 150 MHz while power consumption was only 2.514 W, providing real-time processing capability and low power consumption.
Cited by 0
Abdelkader El Kamel · HAL (Le Centre pour la Communication Scientifique Directe) · 2008
Cited by 0
Matěj, Aleš · Brno University of Technology Digital Library (Brno University of Technology) · 2018
Cílem této práce je první navrhnout a implementovat aplikaci pro vestavěné systémy rea-lizující konvoluční neuronovou síť jenž klasifikuje čísla MNIST, ve druhé části pak optima-lizovat paměťové a energetické nároky této sítě. Práce v teoretické části popisuje základyneuronových sítí a výpočetní platformy Cortex-M pro vestavěné systémy. Následuje popisimplementace, síť je první vytvořena a naučena pomocí knihovny Theano v Pythonu naPC a poté je převedena do C pro vývojovou desku STM32F429 Discovery, kde je následnéoptimalizována. Optimalizace je zaměřena na konvoluci, skalární součin a formát uloženívah a biasů sítě.
Cited by 0
Xiling Luo · 2006
Aiming at the shortage of traditional AFTN gateway,a method of design and implementation of an embedded gateway was proposed.The gateway's architecture was introduced in detail,which was based on VxWorks(a Real-Time Operating System).Several key technologies used in the embedded AFTN gateway such as hot standby and gateway configuration were deeply analyzed.
Cited by 0
Krzysztof Iniewski · 2012
Cited by 6
Ledina Karter, Linda Ferhati, Igli Tafa et al. · 2015
The main objective of this paper is the evaluation of security features in TPM implementations. Nowadays security is very important, especially for those who keep important information on their computers, such as passwords, bank accounts and certificates. TPM can help to keep the information protected from possible adversaries. In order to trust in a TPM-enabled computing device, one must be sure that it really secures the stored information in it. In this paper are investigated security features and concerns of TPM and also is performed an evaluation of the advantages and disadvantages its shows. The evaluation is based on different experimental results which include TPM implementation and capabilities involving various software and computers equipped with embedded TPM.
Cited by 2
Gyun Deuk Park, Joong Soo Chung, Kwang Wook Jung · Journal of the Korea Society of Computer and Information · 2013
본 논문에서는 교육용 임베디드 라우터 실습장비 설계를 제시하였다. 교육용 임베디드 라우터 실습장비는 사용자가 인터넷 환경에서네트워크 구성과 임베디드 라우터 프로그래밍 실습 교육을 할 수 있도록 설계 및 구현되었다. 정적 및 동적 라우팅 프로토콜과 방화벽을 지원하는 라우터 기술 교육용 시스템 설계를 임베디드 환경에서 이더넷 인터페이스를 바탕으로 제시하였다. 개발 환경으로는 CPU는 PXA255, 디버깅 환경은 ADS 1.2, RTOS는 uC/OS-ii, 개발 언어는 C 언어를 사용하였다. 교육 과정으로는 제공된 정적 및 동적 라우팅 프로토콜과 방화벽 프로그램을 컴파일 및 로딩이후 데모 동작의 ping 처리과정으로 이들 기능의 점검 후 ping 패킷 처리의 성능도 살펴보았다. 이후 데모 기능과 유사하게 동작하는 프로그래밍을 하도록 기술 교육을 단계별로 진행시키도록 하였다. 즉, 정적 및 동적 라우팅 프로토콜과 패킷 필터링에 따른 프로그래밍의 완성 및 이의 검증을 수행하도록 하였다. This paper presents the design of the educational router system. This system is designed and implemented to support network configuration and embedded programming technology of the user on Internet. Not only Static routing protocol but also a kind of dynamic routing protocols such as OSPF and RIP and firewall have been programmed for education based on ethernet interface. ADS 1.2 as debugging environment, uC/OS-ii as RTOS and C language as development language are used. The educational procedures is compile, loading of static routing protocol, a kind of dynamic routing protocols such as OSPF and RIP and firewall program already supplied. Thereafter the verification is checked by using "ping" test to allow for demo operation such as hands-on training procedure. Finally programming procedure similar with demo operation of static routing protocol, a kind of dynamic routing protocols such as OSPF and RIP and packet filtering function is educated step by step.
Cited by 2Open access
Pedram Ghazi · Tampere University Institutional Repository (Tampere University) · 2018
In this work, our focus is on the real-time development of a smile recognition system on low resource computational devices utilizing deep learning algorithms which could be simply further developed to address issues in mentioned areas. \nWe have primarily used the Looking at People (LAP) dataset for training and testing various neural network architectures. Images in this dataset have been pre-processed at first by acts of cropping around the facial area and face alignment. Then six pre-trained deep learning network architectures were finetuned for this purpose. \nThe fine-tuned models were deployed on Nvidia’s embedded platform and we were employing an asynchronous design to provide smoother frame rate through parallelization and multithreading. Accuracy and speed of these models were retrieved letting us compare them to each other and choose the most suitable ones for this task. Our research shows that modern low complexity architectures could almost reach the older or bulkier ones’ performance.
Cited by 0Open access
David Donari, Leonardo Damian Ordinez, Rodrigo Santos et al. · 2010
Cited by 0
Xuepei Wu · DR-NTU (Nanyang Technological University) · 2011
Cited by 0
Enathu Kanchipuram, Enathur Kanchipuram · 2014
The main objective of Research is to implement embedded agile methodology using microcontroller. In earlier years agile methods have seen, individually, earn a worldwide following. The agile methods are used to indicate an advance in good practices of software development life cycle, but the advantages of agile methods changes across the different regions of software development. Embedded systems is an best illustration of a software development regime in which implementation of agile methods can be challenging, and the pros of using agile methods may not be as marked as in other systems of software development. This paper explains how the different aspects of embedded software development affect the usage of agile methods to field of embedded. Developers,stakeholder,business and end user should see developed schedule performance and product quality. Developers should get capablity of regular feedback of iteractive development Tdd and spend a lot less time finding errors. Stakeholder, Business should see imporved certain and visible fact based of management data.Even though the whole result of using agile methods in embedded system software development is an improving efficiency, cautious method is needed to get the potential benefits.
Cited by 0
Guang Dong, Ming Fang, Wei He, Yuhang Wang · Bulletin of Miscellaneous Information (Royal Gardens Kew)
This paper introduces the software architecture of home gateway system based on embedded Linux technology, using Socket programming technology and implementing exchange between the RS232 data within the system and external Internet data. This system completes the database design on embedded home gateway using SQLite architecture, and implements the application of the SQLite embedded database on home gateway. Analysis of TCP/ IP protocol, according to the embedded home gateway protocol, by cutting the TCP/ IP protocol layer, the system implements the transplant of TCP/ IP protocol stack on embedded home gateway. Web server is successfully ported, and embedded Linux operation system is ported to home gateway platform.
Cited by 0
Vida Kianzad, Shuvra S. Bhattacharyya · 2001
In this paper, we address two key trends in the synthesis of implementations for embedded multiprocessors -(1) the increasing importance of managing interprocessor communication (IPC) in an efficient manner, and (2) the acceptance of significantly longer compilation time by embedded system designers.The former aspect is especially evident in the increasing interest among embedded system architects in innovative communication architectures, such as those involving optical interconnection technologies, and hybrid electro-optical structures [8,19].The latter aspect -increased compile-time tolerance -results because embedded multiprocessor systems are typically designed as final implementations for dedicated functions.While multiprocessor mapping strategies for general-purpose systems are usually designed with low to moderate complexity as a constraint, embedded system design tools are allowed to employ more thorough and time-consuming optimization techniques [13].
Cited by 3
Leomar Soares da Rosa Junior · Lume (Universidade Federal do Rio Grande do Sul) · 2004
Cada vez mais equipamentos eletrônicos digitais têm sido fabricados utilizando um sistema operacional embarcado. Por razões de custo, estes sistemas operacionais são implementados sobre um hardware com os requisitos mínimos para atender as necessidades da aplicação. Este trabalho apresenta um estudo sobre a viabilidade de implementação de suporte a multitarefa sobre a arquitetura FemtoJava, um microcontrolador monotarefa dedicado a sistemas embarcados. Para tanto, o suporte de hardware necessário é adicionado à arquitetura. Também são implementados dois escalonadores de tarefas diretamente em bytecodes Java, visando à otimização de área e o compromisso com desempenho e consumo de energia. Modificações no ambiente de desenvolvimento e uma ferramenta de relocação de endereços são propostas, objetivando a utilização dos escalonadores de tarefas implementados junto ao fluxo de desenvolvimento existente. Por fim, uma análise é realizada sobre o impacto que a capacidade de multitarefa produz no sistema em termos de desempenho, consumo de área e energia.
Cited by 0Open access
Su, Xiao · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2023
Digital filters have been widely used in signal processing, to reduce or remove unwanted signals of different types, such as noise, and interference, and to enhance or keep desired signals. They are implemented as algorithms on an embedded system (a microcontroller) or a computer. Digital filters are of two different types, finite impulse response (FIR) and infinite impulse response (IIR) filters, each of which can perform different filter functions, such as low-pass (LP), high-pass (HP), band-pass (BP), and band-stop (BS) filtering.The purpose of this thesis project is to develop a filter platform based on an embedded system, which can be used to provide both FIR and IIR filters for LP, HP, BP and BS filtering according to user's needs and specifications. For this purpose, a prototype has been made. It consists of an analog circuit functioning as an anti-aliasing and reconstruction filter, a 32-bit AVR microcontroller with eight analog-to-digital conversions (ADC) channels and two digital-analog conversion (DAC) channels, and a personal computer (PC). On the microcontroller, Digital filters are implemented which can be two or more different filters connected to two inputs (ADCs) and two outputs (DACs). On the PC a user interface is implemented on which the user can specify digital filter types (FIR or IIR), filtering functions (LP, HP, BP and BS) as well as filter order, cutoff frequencies, and the connection of multiple filters in serial or parallel. The prototype has been tested and evaluated. The user interface functions well, sending the user's filter specifications to the microcontroller. The FIR filters for different filtering functions are shown to work satisfactorily. Due to the limited amount of computation, the IIR filter in this case is only of the third order, but the output can still detect the change in signal strength quite clearly. The connections of FIR or IIR filters in series or in parallel through a single channel have been implemented, and they have been shown to work correctly. The combination of FIR and IIR in dual-channel configuration is not successful due to time restriction, and further work for this is needed in the future development.
Cited by 0Open access