Peter Marwedel · 2008
Abstract | This tutorial responds to the increasing use of embedded processors for implementing systemson-a-chip. We will provide an introduction to embedded processors and we will show that current compilers do not provide the required e ciency. We will giveanoverview over new compiler optimization techniques, which aim at making assembly language programming for embedded software obsolete. Finally, we will present techniques for retargeting compilers to new architectures. One of the approaches closes the gap between electronic CAD and compiler generation.
Cited by 0
Steve Heath · Elsevier eBooks · 2002
Cited by 0
2007
Cited by 32
Stefan Tillich, Mario Kirschbaum, Alexander Szekely · 2010
Resistance against side-channel analysis (SCA) attacks is an important requirement for many secure embedded systems. Microprocessors and microcontrollers which include suitable countermeasures can be a vital building block for such systems. In this paper, we present a detailed concept for building embedded processors with SCA countermeasures. Our concept is based on ideas for the secure implementation of cryptographic instruction set extensions. On the one hand, it draws from known SCA countermeasures like DPA-resistant logic styles. On the other hand, our protection scheme is geared towards use in modern embedded applications like PDAs and smart phones. It supports multitasking and a separation of secure system software and (potentially insecure) user applications. Furthermore, our concept affords support for a wide range of cryptographic algorithms. Based on this concept, embedded processor cores with support for a selected set of cryptographic algorithms can be built using a fully automated design flow.
Cited by 14
Jason Wong · Research Repository (Delft University of Technology) · 2002
Cited by 2
2008
Designing multi-threaded and multi-core processor architectures has become one of the most challenging projects for computer scientists in the last few years. But not only the design of such architectures for desktop computers, servers, or high performance computing (HPC) clusters has been investigated in a sophisticated manner, also in the area of embedded systems, researchers have started to investigate the possibilities of using the newly acquired knowledge to implement multi-core processors for embedded systems. Unfortunately, such streamlined computers bring a whole lot of constraints to the design of processor in general. Just to name some of them, scientists have to deal with less memory available, less possibilities to cool the evolving heat, and last but not least, the most important design criteria means to be that embedded systems cannot provide the integrated processors with the same amount of power as the above mentioned systems (like servers or HPC clusters). But these are only a few of the main problems scientists were faced with in the early days of processor design, especially the design of multi-core processors for embedded systems. This paper will give the reader a profound overview of the main architectural approaches, currently used in field implementations and they will also be discussed. Furthermore the reader will be presented some of the available real life implementations of the various architectural approaches, which will as well be discussed in detail by pointing out their assets and drawbacks. 1 1
Cited by 0
Nagarajan Kandasamy, Sherif Abdelwahed, See Profile et al. · 2008
Cited by 0
Panit Watcharawitch, C Panit Watcharawitch · 2003
Conventional embedded microprocessors have traditionally followed the footsteps of highend processor design to achieve high performance. Their underlying architectures prioritise tasks by time-critical interrupts and rely on software to perform scheduling tasks. Single threaded execution relies on instruction-based probabilistic techniques, such as speculative execution and branch prediction. These techniques might be unsuitable for embedded systems where real-time performance guarantees need to be met [1, 2]. Multithreading appears to be a feasible solution with potential for embedded processors [3]. The multithreaded model benefits from sequential characteristic of control-flow and concurrency characteristic of data-flow [4]. Thread-level parallelism has a potential to overcome the limitations of insufficient instruction-level parallelism to hide the increasing memory latencies. Earlier empirical studies on multithreaded processors [5, 4, 6, 7, 3] demonstrated that exploiting thread-level concurrency not only offers latency tolerance, but also provides predictable performance gain. A MulTithreaded Embedded Processor (MulTEP) is designed to provide high performance thread-level parallelism, real-time characteristics, a flexible number of threads
Cited by 0
Prof. Dr. S. Vassiliadis, Prof. Ir. G. L, Reijns Technische et al. · 2001
Cited by 0
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana · 2001
Abstract. It is well-known that the main disadvantages associated with recon-figurable hardware are long reconfiguration latencies, high opcode space requirements, and complex decoder hardware. To overcome these disadvantages, weuse microcode since it allows emulation of "complex " operations which are performed using a sequence of smaller and simpler operations. Microcode is used tocontrol the reconfiguration of the reconfigurable hardware, either online or offline, and the execution on the reconfigurable hardware. Due to the multitude ofmicrocodes and their sizes, it is not feasible to provide on-chip storage for all microcodes. Consequently, the loading of microcode into a limited on-chip storagefacility is becoming increasingly more important. In this paper, we present two methods of loading microcodes into such an on-chip storage facility. 1 Introduction Traditionally, embedded processor design was very much similar to microcontrollerdesign. This meant that for each targeted set of applications, an embedded processor was designed in specialized hardware (commonly referred to as Application SpecificIntegrated Circuits (ASICs)). In the early nineties, we were witnessing a shift in the embedded processor design approach fueled by the need for faster time-to-market. Thisresulted in the utilization of programmable processor cores that were augmented with specialized hardware units, which were still implemented in ASICs. This meant thattime-critical tasks were implemented in specialized hardware units while other less time-critical tasks were implemented in software to be run on the programmable pro-cessor core [1]. This approach allows a programmable processor core to be re-used for different sets of applications without redesigning it. This leaves only the specializedhardware units to be (re-)designed for the targeted set of applications.
Cited by 0
Torres, Lionel · HAL (Le Centre pour la Communication Scientifique Directe) · 2013
Embedded NVM Workshop, Gardanne, France
Cited by 0
Nikil Dutt, Kiyoung Choi · Computer · 2003
We have all heard about the increasing software content of embedded systems. To those who think of embedded software as autonomous programs hidden deep within the system, plugging away transparently and reliably on dedicated tasks, this increase might suggest that these programs are somehow becoming larger. In reality, the ongoing increases in processor performance let system designers implement in software what previously required dedicated or custom hardware blocks and accelerators. Indeed, given a choice, system designers might actually prefer the flexibility of implementing all embedded applications in software on programmable processors. However, parts of the applications must often run under critical time, performance, power, and cost constraints. Thus, designers have traditionally mapped these segments into custom hardware, such as application-specific integrated circuits (ASICs), or into reprogrammable fabrics, such as field programmable gate arrays (FPGAs). Ever-increasing chip capacities have given rise to configurable processors that offer virtually unlimited choices in core architectures.
Cited by 25
Marwedel, Peter, Goossens, Gert · CERN Document Server (European Organization for Nuclear Research) · 2002
Cited by 0
Sybille Hellebrand, Hans-Joachim Wunderlich · 1996
Cited by 0
Corporate Intel Corp. · 1992
Cited by 3
Dinesh Dasarathan · NCSU Libraries Repository (North Carolina State University Libraries) · 2005
The design of a processor is an iterative process, with many cycles of simulation, performance analysis and subsequent changes. The inputs to these cycles of simulations are generally a selected subset of standard benchmarks. To aid in reducing the number of cycles involved in design, one can characterize these selected benchmarks and use those characteristics to hit at a good initial design that will converge faster. Methods and systems to characterize benchmarks for normal processors are designed and implemented. This thesis extends these approaches and defines an abstract system to characterize benchmarks for embedded processors, taking into consideration the architectural requirements, power constraints and code compressibility. To demonstrate this method, around 25 benchmarks are characterized (10 from SPEC, and 15 from standard embedded benchmark suites - Mediabench and Netbench), and compared. Moreover, the similarities between these benchmarks are also analyzed and presented.
Cited by 0Open access
Sai Pinnepalli · 2004
Embedded processors that are common in electronic devices perform a limited set of tasks compared to general-purpose processor systems. They have limited resources which have to be efficiently used. Optimal utilization of program memory needs a reduction in code size which can be achieved by eliminating unnecessary address computations i.e., generate optimal offset assignment that utilizes built-in addressing modes. Single offset assignment (SOA) solutions, used for processors with one address register; start with the access sequence of variables to determine the optimal assignment. This research uses the basic block to commutatively transform statements to alter the access sequence. Edges in the access graphs are classified into breakable and unbreakable edges. Unbreakable edges are preferred when selecting edges for the assignment. Breakable edges are used to commutatively transform statements such that the assignment cost is reduced. The use of a modify register in some processors allows the address to be modified by a value in MR in addition to post-increment/decrement modes. Though finding the most beneficial value of MR is a common practice, this research shows that modifying the access sequence using edge fold, node swap, and path interleave techniques for an MR value of two has significant benefit. General offset assignment requires variables in the access sequence to be partitioned to various address registers. Use of the node degree in the access graph demonstrates greater benefit than using edge weights and frequency of variables. The Static Single Assignment (SSA) form of the basic block introduces new variables to an access graph, making it sparser. Sparser access graphs usually have lower assignment costs. The SSA form allows reuse of variable space based on variable lifetimes. Offset assignment solutions may be improved by incrementally assignment based on uncovered edges, providing the best cost improvement. This heuristic considers improvements due to all uncovered edges. Optimization techniques have primarily been edge-based. Node-based SOA technique has been tested for use with commutative transformations and shown to be better than edge-based heuristics. Heuristics developed in this research perform address optimizations for embedded processors, employing new techniques that lower address computation costs.
Cited by 0Open access
2008
Abstract – The increasing use of programmable processors as IP blocks in embedded system design creates a need for C/C++ compilers capable of generating efficient machine code. Many of today’s compilers for embedded processors suffer from insufficient code quality in terms of code size and performance. This violates the tight chip area and realtime constraints often imposed on embedded systems. The reason is that embedded processors typically show architectural features which are not well handled by classical compiler technology. This paper provides a survey of methods and techniques dedicated to efficient code generation for embedded processors. Emphasis is put on DSP and multimedia processors, for which better compiler technology is definitely required. In addition, some frontend aspects and recent trends in research and industry are briefly covered. The goal of these recent efforts in embedded code generation is to facilitate the step from assembly to high-level language programming of embedded systems, so as to provide higher productivity, dependability, and portability of embedded software 1. 1
Cited by 0
New Electronics · 2020
Cited by 0
Jan Sjödin, Carl von Platen · 2001
In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted to certain native pointer types. Different pointer types vary in size and cost. For example, it is typically cheaper to use an 8-bit pointer than a 16-bit pointer. The problem is to allocate data and select pointer types in the most effective way. Frequently accessed variables should be allocated in fast memory, and frequently used pointers and pointer expressions should be assigned cheap pointer types. Common practice is to perform this task manually.We present a model for storage allocation that is capable of describing architectures with irregular memory organization and with several native pointer types. This model is used in an integer linear programming (ILP) formulation of the problem. An ILP solver is applied to get an optimal solution under the model. We describe allocation of global variables and local variables with static storage duration.A whole program optimizing C compiler prototype was used to implement the allocator. Experiments were performed on the Atmel AVR 8-bit microcontroller [2] using small to medium sized C programs. The results varied with the benchmarks, with up to 8% improvement in execution speed and 10% reduction in code size.
Cited by 7