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About 5,280 papers for “error floor”

LDPC Error Floor Improvement

Aseel Hameed Majeed · Engineering and Technology Journal · 2012

The error-correcting performance of low-density parity check (LDPC) codes, when decoded using practical iterative decoding algorithms, is known to be close to Shannon limits. In this paper we study the LDPC codes performance when varying code rate, constellation level and the maximum number of iteration, this paper shows better coding gain can be obtained at the cost of higher complexity or higher bit rate. For some cases, due to their inability to reach very low bit error rates (e.g., 10− 12) at low signal-to-noise ratios (SNRs), a consequence the error rate floor phenomenon associated with iterative LDPC decoders is produced. This paper demonstrates that the concatenation system used LDPC as an inner code and the Bose, Chaudhuri, and Hocquenghem codes (BCH) as an outer code can successfully lower the floor. Connecting BCH codes lower the LDPC BER floor by a factor( from 32 to 22) at about SNR (from -1dB to 1.8 dB) with the same overall cod rate(i.e without any reduction in the bandwith efficiency) and restricted few number of iteration ( only 5 iterations).

Cited by 5Open access

Low error floor LT coding algorithm for unequal error protection

Xin SONG, Shuyan NI, Zhe ZHANG et al. · SHILAP Revista de lepidopterología · 2022

Objectives:Rateless LT code is designed to provide an ideal transport protocol for large-scale data distribution and reliable broadcasting.The rateless LT code has three excellent characteristics,namely link adaptation,the code rate can be switched seamlessly, and the feedback method is relatively simple. There is an important application scenario in wireless data transmission, namely unequal error protection (UEP) data transmission. As the first achievable rateless code,the rateless LT code can be conveniently used in conjunction with the UEP algorithm to realize adaptive data transmission.However,the conventional UEP-LT code algorithm has problems such as high error floor and poor convergence performance in the additive white Gaussian noise(AWGN)channel.Therefore,an improved systematic UEP-LT coding scheme is designed in this paper. Methods: This paper considers designing independent systematic UEP-LT codes for AWGN channels.A design method of check distribution matching this scheme is given,and a coding scheme characterized by segmentation is proposed.In this scheme,systematic nodes connected with information nodes one by one are designed to provide non-zero log-likelihood ratio (LLR) information from the channel.After that, there is a fixed number of check nodes,that is,the fixed segment.The check node of this segment is only connected to the important bit(MIB),and its purpose is to make the MIB the closest to the successful decoding state.The final part of the coding scheme is the rateless coding segment. The check nodes in this segment will select MIB or least important bit (LIB) as neighbor nodes,and the proportion of check nodes connected to MIB and LIB can be flexibly adjusted,so that the MIB is always successfully decoded before the LIB.This paper also proposes a degree distribution design model adapted to the above coding scheme.This design model aims to provide a sufficiently wide extrinsic information decoding tunnel for the MIB,and an open and not too narrow decoding tunnel for the LIB.When only the fixed segment is transmitted, the degree distribution to be designed should bring the MIB closest to the successful decoding state.When starting to transmit the rateless segment,the degree distribution to be designed should ensure that the MIB is recovered correctly as soon as possible,and the decoding tunnel of the MIB is wide enough when the LIB is in a critical decoding state. Under the above constraints, the designed check degree distribution can provide the MIB with better convergence performance than the LIB. Results:Taking the code length K equal to 6000 as an example to simulate,and the results are as follows.(i)When the signal-to-noise ratio(SNR) is low,the MIB in this scheme has the lowest error floor.For example, when the reciprocal code rate <sup>-1</sup>=2.05, compared with the reference scheme, the bit error rate (BER) of the MIB proposed in this paper is reduced by nearly an order of magnitude,and the lowest value can reach the order of 10<sup>-7</sup>. In addition,the scheme in this paper also has the optimal convergence performance,that is,it can enter the BER waterfall region with a small coding overhead. Taking 10<sup>-6</sup>as the BER standard, the overhead saved by the proposed scheme is at least 10% of the code length K,which reflects the advantages of the proposed scheme.(ii) When the SNR is high,whether it is the MIB or the LIB,the BER performance of the proposed scheme is optimal. For the MIB,the BER of the proposed scheme is always more than an order of magnitude lower than the reference scheme. If 10<sup>-6</sup>is considered as the BER standard, the overhead saved by this scheme is about 7% of the code length K.However,if 10<sup>-7</sup>is further considered as the BER standard,the overhead saved by this scheme is about 15% of the code length K.This means that when the SNR increases,the performance improvement of the proposed scheme is higher than that of the reference scheme. Conclusions: In this paper, a systematic unequal error protection LT coding scheme is designed, and a check degree distribution design model suitable for this scheme is constructed to solve the problem of high error floor existing in the conventional UEP-LT algorithm in the AWGN channel.The main idea of this scheme is to design fixed coding segments,rateless coding segments and systematic node segments and transmit them in sequence.The advantage of this scheme is that it can provide non-zero LLR information as early as possible for information nodes, and make the MIB and the LIB obtain different and flexibly adjustable average degrees.In addition,based on the extrinsic information transfer(EXIT)chart,the check degree distribution is designed for the fixed segment and the rateless segment,so that the MIB can obtain the optimal protection performance,and the convergence performance of the LIB can be improved as much as possible. In the follow-up work, it can be considered to design a check degree distribution model that can more closely approximate the channel capacity, so as to further improve the coding efficiency of the scheme when the BER standard is given.

Cited by 0Open access

High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders

Sina Tolouei · 2014

This thesis explores hardware implementation of low error floor and high speed low-density parity-check (LDPC) decoders. At first, a novel partially-parallel implementation of a protograph-based quasi-cyclic (QC) LDPC decoder, using a new column-layered message-passing schedule is presented. A new design for serial-input check nodes and switch networks, results in lower hardware complexity while having a higher throughput and comparable latency in comparison with all existing partiallyparallel architectures.

Cited by 2Open access

An error floor in tone calibrated transmission

J.K. Cavers · NASA STI Repository (National Aeronautics and Space Administration) · 1988

Use of a low level pilot tone has been shown to eliminate the error floor in fading channels. This paper demonstrates that non-idealities in the receiver's pilot tone filter cause reappearance of the error floor. It also presents the bit error rate (BER) in closed form, in contrast to the multidimensional numerical integration of previous work.

Cited by 0Open access

Controlling the Error Floor in LDPC Decoding

Shuai Zhang, Christian Schlegel · arXiv (Cornell University) · 2012

The error floor of LDPC is revisited as an effect of dynamic message behavior in the so-called absorption sets of the code. It is shown that if the signal growth in the absorption sets is properly balanced by the growth of set-external messages, the error floor can be lowered to essentially arbitrarily low levels. Importance sampling techniques are discussed and used to verify the analysis, as well as to discuss the impact of iterations and message quantization on the code performance in the ultra-low BER (error floor) regime.

Cited by 0Open access

Bit Error Floor of MPSK in the Presence of Phase Error

Yeonsoo Jang, Jin-Woo Jeong, Dongweon Yoon · IEEE Transactions on Vehicular Technology · 2015

In mobile communication systems, one of the most significant factors of the bit-error-rate (BER) performance degradation of M-ary phase-shift keying (MPSK) is random phase error caused by phase-locked loop (PLL) or imperfect channel estimation. For high-signal-to-noise-power-ratio (SNR) regions, the effect of random phase error on BER performance becomes dominant and results in an irreducible BER called the bit error floor. In this paper, we derive a bit error floor expression of Gray-coded MPSK when random phase error exists and show that the bit error floor in fading channels converges to the bit error floor in additive white Gaussian noise (AWGN) channels. The derived expression is simple and accurate in the error floor region; hence, it can offer a convenient way to calculate the irreducible BER of MPSK in the presence of phase error.

Cited by 26

Error Floor Analysis of LDPC Row Layered Decoders

Ali Farsiabi, Amir H. Banihashemi · IEEE Transactions on Information Theory · 2021

In this paper, we analyze the error floor of quasi-cyclic (QC) low-density parity-check (LDPC) codes decoded by the sum-product algorithm (SPA) with row layered message-passing scheduling. For this, we develop a linear state-space model of trapping sets (TSs) which incorporates the layered nature of scheduling. We demonstrate that the contribution of each TS to the error floor is not only a function of the topology of the TS, but also depends on the row layers in which different check nodes of the TS are located. This information, referred to as TS layer profile (TSLP), plays an important role in the harmfulness of a TS. As a result, the harmfulness of a TS in particular, and the error floor of the code in general, can significantly change by changing the order in which the information of different layers, corresponding to different row blocks of the parity-check matrix, is updated. We also study the problem of finding a layer ordering that minimizes the error floor, and obtain row layered decoders with error floor significantly lower than that of their flooding counterparts. As part of our analysis, we make connections between the parameters of the state-space model for a row layered schedule and those of the flooding schedule. Simulation results are presented to show the accuracy of analytical error floor estimates.

Cited by 10

Error Floor Analysis of LDPC Column Layered Decoders

Ali Farsiabi, Amir H. Banihashemi · IEEE Communications Letters · 2021

In this letter, we analyze the error floor of column layered decoders, also known as shuffled decoders, for low-density parity-check (LDPC) codes under saturating sum-product algorithm (SPA). To estimate the error floor, we evaluate the failure rate of different trapping sets (TSs) that contribute to the frame error rate in the error floor region. For each such TS, we model the dynamics of SPA in the vicinity of the TS by a linear state-space model that incorporates the information of the layered message-passing schedule. Consequently, the model parameters and the failure rate of the TS change as a result of the change in the order by which the messages of different layers are updated. This, in turn, causes the error floor of the code to change as a function of scheduling. Based on the proposed analysis, we then devise an efficient search algorithm to find a schedule that minimizes the error floor. Simulation results are presented to verify the accuracy of the proposed error floor estimation technique.

Cited by 0Open access

Low Error Floor Concatenated LDPC for MIMO Systems

Lamia Berriche, Areej Al · International Journal of Advanced Computer Science and Applications · 2017

Multiple-Input and Multiple-Output, or MIMO is the use of multiple antennas at both the transmitter and receiver to improve communication performance. MIMO technology has attracted attention in wireless communications; because it offers significant increases in data throughput and spectral efficiency without additional bandwidth or increased transmit power. To achieve the mentioned above performance Bit Error Rates (BER) should be low. For this reason efficient encoding and decoding algorithms should be used. MIMO systems rely on error-control coding to ensure reliable communication in the presence of noise. Forward Error Correction Codes (FEC) such as convolutional and block codes were investigated for MIMO systems. Low Density Parity Check (LDPC) shows good performance except that an error floor may appear at high Signal to Noise Ratio (SNR). In this work we propose a concatenated error control code that reduces the error floor of LDPC codes suffering from error floor. The proposed scheme is a good candidate for high rates real time communication since it reduces the decoding latency as well.

Cited by 4Open access

Will the real error floor please stand up?

Xiaojie Zhang, Paul H. Siegel · 2012

In this paper we continue our study of the influence of message saturation and quantization on the error-rate performance of iterative, message-passing decoders for low-density parity-check (LDPC) codes. We extend our previous analytical results for the min-sum algorithm (MSA) and its variants to the sum-product algorithm (SPA), demonstrating the significant impact of message saturation on the appearance and location of error floors. Simulation results for selected LDPC codes on the binary symmetric channel (BSC) and the additive white Gaussian noise channel (AWGNC) confirm that the benefits of a quasiuniform quantization scheme, already observed in the context of MSA decoding, apply also to SPA-based decoding.

Cited by 7

Error Floor Analysis of Quasi-Cyclic LDPC and Spatially Coupled-LDPC Codes and Construction of Codes with Low Error Floor

Sima Naseri · 2021

Forward error-correcting (FEC) codes play an important role in transmitting data with extremely high reliability through modern communication systems. Many applications such as optical communication channels require a very low error rate when transmitting data. In this thesis, we study the design and analysis of low-density parity-check (LDPC) codes in general and spatially coupled (SC) LDPC codes in particular. At first, we analyze the error floor performance of finite-length protographbased spatially coupled LDPC codes in terms of their design parameters. We conduct a comprehensive analysis to show that the parameter syndrome former memory (m) plays the main role in the average number of cycles and trapping sets in the Tanner graph of finite-length SC-LDPC codes. This, in fact, gives an insight into the error floor performance of protograph-based SC-LDPC codes, and demonstrates the superiority of these codes in the error floor region, compared to their block code counterparts.

Cited by 2Open access

On the irreducible error floor in fast fading channels

Brian Hart, D.P. Taylor · IEEE Transactions on Vehicular Technology · 2000

In fast fading channels without pilot information, existing receiver structures exhibit an "irreducible error floor," where their bit error rate (BER) levels out at high signal-to-noise ratio (SNR). This is even observed in practical maximum likelihood sequence detectors (i.e., MLSDs with certain approximations, in order to achieve finite per-symbol complexity). The conditions for optimality and for an error floor are examined in detail. We find that the standard receiver design choices induce an error floor unless the channel has very specific properties.

Cited by 8

On the Irreducible Error Floor in Fast Fading Channels

Brian Hart Desmond, Brian D. Hart, Desmond P. Taylor · 1998

In fast fading channels without pilot information, existing receiver structures exhibit an error floor. This is observed even in practical implementations of maximum likelihood sequence detectors (MLSDs) [1,2]. In this paper, the conditions for optimality and for an error floor are examined in detail. We find that all finite-complexity receivers must exhibit an error floor unless the channel has very specific properties. Thus the error floors found in [1,2] are explained in a more rigorous manner.

Cited by 0

LDPC Code Density Evolution in the Error Floor Region

Brian K. Butler, Paul H. Siegel · arXiv (Cornell University) · 2014

This short paper explores density evolution (DE) for low-density parity-check (LDPC) codes at signal-to-noise-ratios (SNRs) that are significantly above the decoding threshold. The focus is on the additive white Gaussian noise channel and LDPC codes in which the variable nodes have regular degree. Prior work, using DE, produced results in the error floor region which were asymptotic in the belief-propagation decoder's log-likelihood ratio (LLR) values. We develop expressions which closely approximate the LLR growth behavior at moderate LLR magnitudes. We then produce bounds on the mean extrinsic check-node LLR values required, as a function of SNR, such that the growth rate of the LLRs exceeds that of a particular trapping set's internal LLRs such that its error floor contribution may be eliminated. We find that our predictions for the mean LLRs to be accurate in the error floor region, but the predictions for the LLR variance to be lacking beyond several initial iterations.

Cited by 1Open access

Constraining LDPC degree distributions for improved error floor performance

S.J. Johnson, S.R. Weller · Figshare · 2006

The error floor performance of finite-length irregular low-density parity-check (LDPC) codes can be very poor if code degree distributions are chosen to optimize the threshold performance. In this paper we show that by constraining the optimization process, a balance between threshold and error floor performance can be obtained. The resulting degree distributions give the best threshold performance subject to some minimum requirement on the error floor.

Cited by 2Open access

A Novel LT Encoding Algorithm with Low Error Floor

Xin Song, Tuofeng Lei, Lingfeng Cheng et al. · 2021

In this paper, an improved encoding scheme for LT codes is designed to reduce the error floor. The main idea of the proposed LT code is to classify the information nodes according to their degrees. Then the low-degree information nodes will be forced to frequently connect to check nodes, which enables all information nodes to obtain enough degrees to be restored successfully. Besides, the information degree distribution and convergence behavior of the proposed scheme are analyzed. Simulation results show that the proposed LT code can significantly reduce the error floor, and outperform the other two improved schemes, particularly for short length codes.

Cited by 0

BER and Error-Floor Calculation for Multi-Access PCTH

Mb No, G. M. Maggie, D. C. Laney et al. · 2016

and ^^o^^^oX^^^^sXrue6 as an official Department of the Army position, policy or decision, unless so designated by other documentation. 12 a. DISTRIBUTION / AVAILABILITY STATEMENT Approved for public release; distribution unlimited. 12 b. DISTRIBUTION CODE 13. ABSTRACT (Maximum 200 words) Pseudo-Chaotic time hopping (PCTH) is a recently proposed modulation scheme for UWB impulse radio. PCTH exploits concepts from symbolic dynamics to generate aperiodic spreading sequence. 14. SUBJECT TERMS PCTH, modulation, UWB impulse radio, bit error rate, Gaussian noice channel

Cited by 0