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About 1,548 papers for “hardware description languages”

Analog hardware description languages

R.A. Saleh, David L. Rhodes, E. Christen et al. · 2002

With the growing trend in ASIC design to include more analog functions on chip, various design support and automation efforts have arisen to address the analog design concerns. Existing hardware description languages have been widely used for design representation, documentation and transfer mainly in the digital domain, with standards such as VHDL being fairly mature. In this paper we present two efforts that are underway in developing standardized analog hardware description languages. One of these is a new language called MHDL for analog and mixed-signal representation while the second is aimed at providing analog extensions to the existing VHDL standard.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 26

Hardware Description Languages (HDLs)

Prashant Kumar, Ravi Mishra · 2013

In this paper, the implementation of software module using &amp;apos;VHDL &amp;apos; for Xilinx FPGA (XC2S30) based PID controller for DC motor speed control system is presented. The tools used for building and testing the software modules are Xilinx ISE 9.1i and ModelSim XE III 6.3c. Before verifying the design on FPGA the complete design is simulated using Modelsim Simulation tool. A test bench is written where, the set speed can be changed for the motor. It is observed that the motor speed gradually changes to the set speed and locks to the set speed.

Cited by 0

Programming Languages for Hardware Description

P. Robinson, J. Dion · 20th Design Automation Conference Proceedings · 1983

This paper describes work done as part of a design automation system for gate arrays. The system provides no hardware description language and circuits are described in the same language in which the system is implemented, Modula-2. We claim that modern programming languages are sufficiently general to be good hardware description languages, and that a design automation system which is based on this principle will be simpler and more extensible than one based on a specialized hardware description language.

Cited by 2

Types and Hardware Description Languages.

Tim Sheard · 2007

Hardware description systems could benefit from advances in programming language design. Recent research, in the area of rich type systems suggests hardware description languages could use types to (1) structure, (2) guarantee correctness, and (3) track properties of hardware descriptions. In this paper, we use the language Ωmega to illustrate these points. 1

Cited by 0

Hardware description languages for ALECSIS simulator

M. Damnjanovic, Z. Dimic, Vančo Litovski et al. · 2002

There are two possibilities for describing the system which could be simulated by our new hybrid simulator ALECSIS: AleC++ and VHDL. Both HDLs are described and their capabilities are compared in this paper.

Cited by 3

Testing Stand Using Hardware Description Languages

Ursan George-Andrei, Plopa Olga, Ursan Maria · 2021 International Conference on Electromechanical and Energy Systems (SIELMEN) · 2021

HDL (Hardware Description Languages) is really important tool for all digital designers. After they have learned about Verilog or VHDL (the abbreviation for Very High Speed Integrated Circuit Hardware Description Language) System, digital designers will be capable to detail digital systems much quicker than if they would have to create all entire schematics. The HDLs are used for simulation and synthesis. It is very important to involve students passionate about digital design to use such modern languages because they can use them successfully in their future career. This paper aims to present an HDL-based test stand that can be implemented using a Nexys2 circuit board which is a complete, ready-to-use circuit development platform based on a Xilinx Spartan 3E FPGA (Field Programmable Gate Array). The Nexys2 board incorporates several input devices, output devices, and data ports, allowing various designs to be implemented with no need for any other components. Basically, the test stand will offer the possibility to choose the number of inputs (three or four) and to establish six basic functions that can be selected for verification, the result being displayed using the BCD (Binary Coded Decimal) display system integrated in the board. The inputs will be represented by the set of push buttons available on the board.

Cited by 1

Program Slicing of Hardware Description Languages

Clarke Reps, E. M. Clarke, T. Reps et al. · 1999

. Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in design, simulation, testing, and formal verification. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a description of the resulting tool, and a brief overview of some applications and experimental results. 1 Introduction Hardware description languages (HDLs) are used today to describe circuits at all level...

Cited by 0

Computer hardware description languages—A tutorial

Sajjan G. Shiva · Proceedings of the IEEE · 1979

Just as software designers use high level languages (HLL) to express the algorithms in terms of language statements, digital hard-ware designers use hardware description languages (HDL) to describe the system they are designing. Although HDL's were originated as a medium of precise yet concise description of digital hardware, they have found a variety of applications such as generating user manuals, teaching logic design, acting as an input medium for an automatic design system, etc. This tutorial paper introduces HDL's as useful tools for hardware design and documentation. The capabilities and limitations of HDL's are discussed, along with the guidelines to select an HDL. The directions for future work and an extensive bibliography are provided.

Cited by 29

Hardware description languages in Great Britain

Bulent I. Dervisoglu · Computer · 1974

The use of hardware description languages in British industries and universities is presented here, including both linguistic and graphical forms of representation.

Cited by 1

CHEMFET modelling for hardware description languages

M. Daniel, Michał Szermer, Andrzej Napieralski et al. · 2003

The new standard - VHDL-AMS (Very High Speed Hardware Description Language-Analogue Mixed Signals) was introduced several months ago. The main aim of introducing the new standard is unification of currently existing hardware description languages and (as in case of VHDL) making the libraries of elements that could be accessible by other users or designers. In this paper the presentation of the model of chemical sensor in VHDL-AMS was proposed. Presented description of the model as well as the results of the simulation was compared with the same model described in ELDO with usage of Hdl-A - so-called "quasi-standard" of the hardware description language introduced some years ago by Mentor Graphics.

Cited by 2

Ties that bind [hardware description languages]

Allan Crone · Electronic Systems and Software · 2006

VHDL designers can take advantage of the advanced verification features of SystemVerilog thanks to the bind function in the newer language. One of the most important languages to emerge for advanced design and verification is SystemVerilog. This language offers a rich set of features for testbench automation, applying native assertions, functional coverage and constrained random test generation. These features make SystemVerilog increasingly appealing to VHDL users who have a number of verification-oriented features at their disposal but need to implement a more efficient functional verification methodology for complex designs.

Cited by 0