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About 616 papers for “hardware multithreading”

Hardware support for software controlled multithreading

Aqeel Mahesri, Nicholas J. Wang, Sanjay J. Patel · ACM SIGARCH Computer Architecture News · 2007

Chip multi-processors have emerged as one of the most effective uses of the huge number of transistors available today and in the future, but questions remain as to the best way to leverage CMPs to accelerate single threaded applications. Previous approaches rely on significant speculation to accomplish this goal. Our proposal, NXA, is less speculative than previous proposals, relying heavily on software to guarantee thread correctness, though still allowing parallelism in the presence of ambiguous dependences. It divides a single thread of execution into multiple using the master-worker paradigm where some set of master threads execute code that spawns tasks for other, worker theads. The master threads generally consist of performance critical instructions that can prefetch data, compute critical control descisions, or compute performance critical dataflow slices. This prevents non-critical instructions from competing with critical instructions for processor resources, allowing the critical thread (and thus the workload) to complete faster. Empirical results from performance simulation show a 20% improvement in performance on a 2-way CMP machine, demonstrating that software controlled multithreading can indeed provide a benefit in the presence of hardware support.

Cited by 5

Enabling multithreading executions on the XILINX microkernel with a hardware scheduler

Yasmin Syuhada Harmin, Razali Jidin, Asraf Mohamed Moubark et al. · 2008

Multithreading programming can improve performance of an application especially to reduce processor busy waiting. Typically, threads that have to wait for input/output responses can wait in a queue (sleep queue), allowing other threads to utilize processor, therefore improving system timeliness and throughput. As such an application can be partitioned into several threads that can be executed on either single or multiple processors. Sharing of processors among threads however requires scheduling to ensure fair sharing scheme or to meet a specific execution objective. The scheduling mechanism serves to allocate which threads get to run on a processor alternately according to the adopted sharing scheme. Processor can be relieved of executing the required scheduling task if it can be performed by a hardware entity such as field programmable gate array (FPGA). This paper describes initial design of hardware scheduler and modification of thread manager to support the migration (of thread scheduler into the hardware). The scheduler is designed as an Intellectual Property (IP) core that can be instantiated like any peripheral core. The work is intended to enable multithreading on XILINX microkernel with a hardware thread scheduler instead of Von Neumann stored instruction scheduling execution.

Cited by 0

EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults

Hwisoo So, Moslem Didehban, Yohan Ko et al. · ACM Transactions on Architecture and Code Optimization · 2022

Error resilience is the primary design concern for safety- and mission-critical applications. Redundant MultiThreading (RMT) is one of the most promising soft and hard error resilience strategies because it does not require additional hardware modification. While the state-of-the-art software RMT scheme can achieve a high degree of error protection, our detailed investigation revealed that it suffers from performance overhead and insufficient fault coverage. This paper proposes EXPERTISE, a compiler-level RMT scheme that can detect the manifestation of hardware faults in all processor components. EXPERTISE transformation generates a checker-thread for the main execution thread. These redundant threads are executed simultaneously on two physically different cores of a multicore processor and perform almost the same computations. After each memory write operation is committed by the main-thread, the checker-thread loads back the written data from the memory and checks it against its own locally computed values. If they match, the execution continues. Otherwise, the error flag is raised. In order to evaluate the effectiveness of the proposed solution, we performed soft and hard error injection experiments on all the different hardware components of an ARM Cortex53-like μ-architecturally simulated microprocessor. Based on statistical fault injection campaigns, we have found that EXPERTISE provides 188× better fault coverage with 27% faster performance as compared to the state-of-the-art scheme.

Cited by 3Open access

Hardware and software mechanisms for multithreading in uniprocessors and heterogeneous multiprocessors

Jeffrey P. Bradford, J.A.B. Fortes · Purdue e-Pubs (Purdue University System) · 2001

This thesis proposes, develops, and evaluates hardware and software mechanisms that enhance the efficiency and performance of multithreading in uniprocessors and in heterogeneous multiprocessors. Hardware synchronization mechanisms are shown via simulation to provide a performance improvement between 0% and 400%, depending on the workload and the synchronization frequency, for a constrained simulation model. Further results show the decrease in available parallelism with increasing synchronization overhead. In addition, a VHDL implementation of the functionality required to support hardware synchronization is discussed. Novel context-switch criteria are proposed that allow processors to better tolerate memory-access latency. While this advantage has been discussed previously for multithreaded processors, this work is the first to examine the performance of context-switch criteria that are based on architectural features used to provide some latency tolerance such as out-of-order dispatch and lockup-free caches. Results from a detailed multiprocessor simulator show a performance improvement of up to 35% over no multithreading, although many criteria examined result in a performance decrease. “Virtual Processors” are shown to provide a performance advantage for applications that have been parallelized for a homogeneous multiprocessor executing on a heterogeneous multiprocessor. Three additional modification are also discussed that provide an ease-of-use or ease-of-design advantages: more efficient interrupt support, starting and stopping threads, and entry to the operating system. The performance improvement is measured using several scientific programs (from the SPLASH-2 benchmark suite) and one commercial program (C4.5, a decision tree induction application). This work is the first to use C4.5 as a benchmark application: thus, this thesis presents the first complete characterization of the memory hierarchy behavior of C4.5, presents the first parallelization of decision tree induction optimized for a ccNUMA architecture, characterizes the parallel version, and examines decision tree induction as a possible benchmark application.

Cited by 0

An optimal abstraction model for hardware multithreading in modern processor architectures

T. Madajczak · 2004

This DOI is not currently attached to any metadata records. DOIs can’t actually ever be deleted (they’re persistent), but sometimes our members create DOIs in error. We do have a process to approximate deletion which we follow only in rare cases where the DOI has been genuinely created in error, and most crucially, if the DOI has never been published anywhere online or in print and never otherwise distributed to or communicated with anyone (authors, readers, reviewers, etc.

Cited by 0Open access

Hardware support for fine-grained parallelism and simultaneous multithreading in RISC-V

Recort Bascuas, Pau · QRU Quaderns de Recerca en Urbanisme · 2023

El processadors moderns han d’explotar tots els nivells de paral·lelisme disponibles per a aconseguir el màxim rendiment i ús dels recursos hardware. Aquest projecte es centra en les arquitectures multifil, que executen múltiples fils de codi simultàniament per a saturar recursos hardware compartits. Les arquitectures multifil, però, requereixen de forma natural d’una alta quantitat de paral·lelisme per a executar eficientment. Utilitzarem el model d’execució P-RISC per a extreure paral·lelisme del codi i saturar els recursos d'execució hardware. El model P-RISC afegeix instruccions pròpies i el suport hardware necessaris per a permetre la creació i sincronització de tasques paral·leles amb un overhead molt baix. En aquest projecte, dissenyem i implementem un nucli multifil RISC-V capaç d’executar el model i les instruccions afegides per P-RISC. Implementem un sistema de memòria amb accés en dues fases i l'estenem amb un sistema de cache que redueix el nombre d’accessos en dues fases. Implementem un àrbitre que maximitza el nombre d’instruccions vàlides enviades a les unitats d’execució mitjançant una política de prioritat basada en el nivell d’especulació. La nostra implementació es pot escalar fins a executar 12 fils fer nucli, ha sigut provada en simulació i FPGA, i es pot sintetitzar a 1.1GHz amb tecnologia GlobalFoundries de 22nm. Aconseguim increments en rendiment de 1.4x fins a 10x en comparació a l’equivalent seqüencial en FPGA.

Cited by 0Open access

Evaluating the impact of simultaneous multithreading on network servers using real hardware

Yaoping Ruan, Vivek S. Pai, Erich Nahum et al. · 2005

This paper examines the performance of simultaneous multithreading (SMT) for network servers using actual hardware, multiple network server applications, and several workloads. Using three versions of the Intel Xeon processor with Hyper-Threading, we perform macroscopic analysis as well as microarchitectural measurements to understand the origins of the performance bottlenecks for SMT processors in these environments. The results of our evaluation suggest that the current SMT support in the Xeon is application and workload sensitive, and may not yield significant benefits for network servers.In general, we find that enabling SMT on real hardware usually produces only slight performance gains, and can sometimes lead to performance loss. In the uniprocessor case, previous studies appear to have neglected the OS overhead in switching from a uniprocessor kernel to an SMT-enabled kernel. The performance loss associated with such support is comparable to the gains provided by SMT. In the 2-way multiprocessor case, the higher number of memory references from SMT often causes the memory system to become the bottleneck, offsetting any processor utilization gains. This effect is compounded by the growing gap between processor speeds and memory latency. In trying to understand the large gains shown by simulation studies, we find that while the general trends for microarchitectural behavior agree with real hardware, differences in sizing assumptions and performance models yield much more optimistic benefits for SMT than we observe.

Cited by 31

A study on impacts of hardware changes on performance of different multithreading libraries based on Gem5

Chen Gu · Journal of Physics Conference Series · 2023

Abstract This paper presents a thorough investigation into the performance of various multithreading libraries on different hardware configurations utilizing gem5. The study compares the performance of commonly-used multithreading libraries, including OpenMP, Pthread, TBB, and Dlib, through several benchmarks representing distinct types of workloads. Key hardware factors that directly affect the performance of each library are identified and analyzed. The research findings provide valuable insights and recommendations for selecting an appropriate multithreading library for a given application and hardware platform. Results indicate that the performance of multithreading libraries is influenced by numerous hardware factors, such as L1 cache size, L1 cache associate, L1 cache replacement policy, number of threads, and memory type. The libraries respond differently to these factors, and the performance variability of each library depends on the nature of the workload. The study offers a detailed analysis and valuable insights into the effects of these hardware factors on each library. This study contributes by presenting a comprehensive comparison of several widely used multithreading libraries across numerous hardware configurations, identifying the key hardware factors that influence the performance of each library, and providing insights and recommendations for selecting an appropriate multithreading library for a given application and hardware platform. Ultimately, the study results can help software developers make informed decisions when selecting a multithreading library and optimizing performance for their applications.

Cited by 0Open access

Dynamic Characteristics of Multithreaded Execution in the EM-X Multiprocessor

Hirofumi Sakane Mitsuhisa, Mitsuhisa Sato, Yuetsu Kodama et al. · 1995

Multithreading is known be effective for tolerating communication latency in distributed-memory multiprocessors. Two types of support for multithreading have been used to date including software and hardware. This paper presents the impact of multithreading on performance through empirical studies. In particular, we explicate the performance difference between software support and hardware support for the 80-processor EM-X distributed-memory multiprocessor which we have designed and implemented. The EMX provides three types of hardware supports for fine-grain multithreading including direct remote memory access, fast thread invocation, and dedicated instructions for generating fixed-sized communication packets. To demonstrate the effect of multithreading, we have performed various experiments using micro benchmark programs and MP3D, one of the SPLASH benchmarks. Three types of performance parameters have been measured including processor efficiency, remote memory latency, and network load. Experimental results indicate that the EM-X architecture is highly effective for supporting the multithreading principles of execution through dedicated hardware and software. keywords Multithreading, latency hiding, fine grain communication, direct remote memory access, shared memory benchmark, synthetic workload. 1

Cited by 0

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

Alfonso Rodríguez, A. Otero, Marco Platzner et al. · IEEE Transactions on Computers · 2021

Current edge computing systems are deployed in highly complex application scenarios with dynamically changing requirements. In order to provide the expected performance and energy efficiency values in these situations, the use of heterogeneous hardware/software platforms at the edge has become widespread. However, these computing platforms still suffer from the lack of unified software-driven programming models to efficiently deploy multi-purpose hardware-accelerated solutions. In parallel, edge computing systems also face another huge challenge: operating under multiple conditions that were not taken into account during any of the design stages. Moreover, these conditions may change over time, forcing self-adaptation mechanisms to become a must. This paper presents an integrated architecture to exploit hardware-accelerated data-parallel models and transparent hardware/software multithreading. In particular, the proposed architecture leverages the ARTICo <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> framework and ReconOS to allow developers to select the most suitable programming model to deploy their edge computing applications onto run-time reconfigurable hardware devices. An evolvable hardware system is used as an additional architectural component during validation, providing support for continuous lifelong learning in smart edge computing scenarios. In particular, the proposed setup exhibits online learning capabilities that include learning by imitation from software-based reference algorithms. Experimental results show the benefits of the proposed approach, exposing different run-time tradeoffs (e.g., computing performance versus functional correctness of the evolved solutions), and highlighting the benefits of using scalable data-parallel models to perform circuit evolution under dynamically changing application scenarios.

Cited by 2

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

Rodríguez Medina, Alfonso, Otero Marnotes, José Andrés, Platzner, Marco et al. · UPM Digital Archive (Technical University of Madrid) · 2022

Current edge computing systems are deployed in highly complex application scenarios with dynamically changing requirements. In order to provide the expected performance and energy efficiency values in these situations, the use of heterogeneous hardware/software platforms at the edge has become widespread. However, these computing platforms still suffer from the lack of unified software-driven programming models to efficiently deploy multi-purpose hardware-accelerated solutions. In parallel, edge computing systems also face another huge challenge: operating under multiple conditions that were not taken into account during any of the design stages. Moreover, these conditions may change over time, forcing self-adaptation mechanisms to become a must. This paper presents an integrated architecture to exploit hardware-accelerated data-parallel models and transparent hardware/software multithreading. In particular, the proposed architecture leverages the \ARTICo framework and ReconOS to allow developers to select the most suitable programming model to deploy their edge computing applications onto run-time reconfigurable hardware devices. An evolvable hardware system is used as an additional architectural component during validation, providing support for continuous lifelong learning in smart edge computing scenarios. In particular, the proposed setup exhibits online learning capabilities that include learning by imitation from software-based reference algorithms.

Cited by 0

A hardware operating system kernel for multi-processor systems

Sang‐Gyu Park, Dosun Hong, Soo‐Ik Chae · IEICE Electronics Express · 2008

We propose a hardware operating system kernel (HOSK), which schedules tasks, controls semaphores, and pre-fetches contexts, as a hardware coprocessor in multiprocessor systems. A multiprocessor system can substantially reduce multithreading overheads by using the HOSK together with simplified RISC processors that do not include hardware for multithreading. We implemented an efficient HOSK which requires about 14 ∼ 25K gates. The experimental results show that the multithreading overheads with a HOSK can be reduced to less than 1 percent. Preliminary efforts confirm that this approach is a feasible solution for minimizing the hardware complexity of a multi-processor system.

Cited by 17Open access

Performance Evaluation of Interleaved Multithreading in a VLIW Architecture

S. Suijkerbuijk, P. Stravers, S. Vassiliadis et al. · 2008

Abstract — Interleaved multithreading is a technique in which the processor starts executing a different task when the current thread is stalled. However, whereas different forms of hardware multithreading have been extensively evaluated in superscalar processors, an evaluation of multithreading techniques in a VLIW architecture is frequently missing. The objective of this paper is to determine an efficient method of implementing interleaved hardware multithreading in the TriMedia and evaluate the performance. The TriMedia is a multimedia VLIW processor designed by Philips semiconductors. Currently, multithreading is not implemented in the TriMedia. First, the details of the used interleaved multithreading method are given. After that, the architectural changes that are made in to cycle-accurate simulator of the TriMedia are described. Then, the various test result are presented. Finally we discuss the conclusions that can be drawn from the simulation results. Index Terms — Interleaved multithreading, VLIW processor, TriMedia I.

Cited by 0

Speculative Multithreading

Lecturer Amin Firoozshahian, Brad Schumitsch, Scribe Suzanne Rivoire et al. · 2003

The first paper for this lecture [1] categorizes various options for supporting speculative multithreading in hardware, while the second [2] describes a way to implement it in software without specific architectural support. The class discussion covered the requirements and tradeoffs of software, hardware, and hybrid support for speculative multithreading.

Cited by 0

CSMT: Simultaneous Multithreading for Clustered VLIW Processors

Manoj Gupta, Fermín Sánchez Carracedo, Josep Llosa · IEEE Transactions on Computers · 2009

Simultaneous MultiThreading (SMT) is a well-known technique that improves resource utilization by exploiting thread-level parallelism at the instruction grain level. However, implementing SMT for VLIWs requires complex structures, which is contrary to the VLIW philosophy of hardware simplicity. In this paper, we propose Cluster-level Simultaneous MultiThreading (CSMT) to allow some degree of SMT in clustered VLIW processors with low hardware cost and complexity. CSMT considers the set of operations that execute simultaneously in a given cluster as the assignment unit. To minimize cluster conflicts between threads, a very simple hardware-based cluster renaming mechanism is proposed. The hardware required to implement CSMT is cheap, realistic, and practical for a clustered VLIW processor. An analysis of the hardware required to implement CSMT shows that it is quite scalable, with up to eight threads easily supported at low hardware cost. The experimental results show that CSMT significantly improves performance when compared with other multithreading approaches suited for VLIW. For instance, with four threads, CSMT shows an average speedup of 110 percent over a single-thread VLIW architecture and 40 percent over Interleaved MultiThreading (IMT). In some cases, speedup can be as high as 225 percent over single-thread architecture and 84 percent over IMT.

Cited by 3

Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading

Dean M. Tullsen, Susan J. Eggers, Joel S. Emery et al. · 1996

Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance potential of simultaneous multithreading, based on a somewhat idealized model. In this paper we show that the throughput gains from simultaneous multithreading can be achieved without extensive changes to a conventional wide-issue superscalar, either in hardware structures or sizes. We present an architecture for simultaneous multithreading that achieves three goals: (1) it minimizes the architectural impact on the conventional superscalar design, (2) it has minimal performance impact on a single thread executing alone, and (3) it achieves significant throughput gains when running multiple threads. Our simultaneous multithreading architecture achieves a throughput of 5.4 instructions per cycle, a 2.5-fold improvement over an unmodified superscalar with similar hardware resources. This speedup is enhanced by an advantage of multithreading previously unexploited in other architectures: the ability to favor for fetch and issue those threads most efficiently using the processor each cycle, thereby providing the “best ” instructions to the processor. 1

Cited by 0

Exploiting choice : Instruction fetch and issue on an implementable simultaneous MultiThreading processor

Jack L. Lo, Rebecca L. Stammy · 1996

Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance potential of si-multaneous multithreading, based on a somewhat idealized model. In this paper we show that the throughput gains from simultaneous multithreading can be achieved without extensive changes to a con-ventional wide-issue superscalar, either in hardware structures or sizes. We present an architecture for simultaneous multithreading that achieves three goals: (1) it minimizes the architectural impact on the conventional superscalar design, (2) it has minimal perfor-mance impact on a single thread executing alone, and (3) it achieves significant throughput gains when running multiple threads. Our simultaneous multithreading architecture achieves a throughput of 5.4 instructions per cycle, a 2.5-fold improvement over an unmod-ified superscalar with similar hardware resources. This speedup is enhanced by an advantage of multithreading previously unexploited in other architectures: the ability to favor for fetch and issue those threads most efficiently using the processor each cycle, thereby providing the “best ” instructions to the processor. 1

Cited by 0