N. Krause · UpSpace Institutional Repository (University of Pretoria) · 2016
Wispeco is a growing company and has reached the point where their GS (Gauteng Stockist) storage \nwarehouse does not possess enough storage space to keep up with the growing demand for Wispeco \nproducts. They have now acquired an additional storage warehouse, where all their hardware products will \nbe stored. \nThe processes in the hardware warehouse (or GC warehouse) is currently relatively unstructured, with no \nstandard operating procedures, information management systems or warehouse management systems in \nplace. \nIn order to improve the operations of this warehouse, an analysis of the current operations have been done, \nalong with an investigation of the current available best practices for similar warehouses. In the investigation \nof available best practices the following warehousing techniques were investigated: Setting up stock levels, \nABC analysis, flow within a warehouse, order picking techniques, layout design, and storage assignment. \nFrom the investigation of best-practices the techniques that will best fit the goals of the GC warehouse are a \npicker-to-part system, with a forward-reserve storage allocation approach. The GC warehouse already \noperates with a forward-reserve storage allocation approach and picker-to-part system, but the current \nlocation of the main areas in the warehouse, namely the small store, bulk store, receiving and dispatch areas, \nare increasing the average travel distance of pickers. These areas need to be located according to the amount \nof movement between the areas. \nThe best storage policy for the GC warehouse is a combination of dedicated storage and full-turnover storage, \nitems with a high turnover rate are located in dedicated location close to the dispatch area. \nWhen conducting an ABC analysis it was found that locating items according to their relative impact on sales \nvalue, will be the best strategy for reducing the average picking distance. The relative impact of an item is \ndetermined by multiplying the value of an item with the annual number of sales. When drawing a Paretograph \nfor the relative impact of sales it was discovered that roughly 16.07 % of the items are responsible for \n80% of GC warehouse’s value of sales. The following 15% of the sales value is comprised from the next \n20.54% of items. The final 5% of sales value is from the final 63.39% of items. These three groups will be \nknown as groups “A”, “B” and “C”. \nThe proposed receiving process, along with the use of an inspection sheet will ensure that incorrect products \nor in accurate quantities are not accepted into the warehouse. The proposed dispatch process, along with a \npicking slip, which indicates the product code, quantities and location of the item that needs to be picked, the \namount of incorrect picks will decrease, along with inaccurate shipments to customers. \nIt was determined that proposed layout 3 is the best layout for the GC warehouse, because It fulfils the most \nimportant criteria of the warehouse. \nWhen comparing the available storage space in the GC warehouse with the required storage space, it was \ndetermined that the warehouse does consist of sufficient space for all the Hardware products.
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Guoqi Xie, Yawen Zhang, Renfa Li et al. · 2023
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Brian Matthew Fahs · 2005
Dynamic instruction count and instruction-level parallelism (ILP) are two limiting factors for high performance computing. Processor designers typically attack these limit-ing factors through processor frequency scaling, and by creating superscalar processors to leverage the inherent ILP in applications. This dissertation adopts a complementary ap-proach of attacking these two factors by using integrated dynamic optimization hardware to directly reduce dynamic instruction count and increase ILP. On a broad level, we describe the relationship between well-known compiler opti-mization concepts and hardware-implemented optimizations. We define and explore two hardware-centric dynamic optimization paradigms: continuous optimization and discrete optimization. Continuous optimization optimizes instructions in the processor pipeline prior to execution. It is primarily useful for reducing processor resource contention and increasing ILP. Discrete optimization captures reusable chunks of the dynamic instruc-tion stream, optimizes them, and then sequences them back into execution. Its primary benefits come from reducing instruction count and increasing ILP. The benefits of these two models are mostly orthogonal, and, therefore, they can be combined to provide larger
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Gerlach, Thore Thassilo · bonndoc (University of Bonn) · 2025
Quantum Optimization (QO) is emerging as a promising approach to tackle hard combinatorial optimization problems by leveraging the unique computational properties of quantum hardware. In recent years, QO has gained traction in Machine Learning (ML), where problems such as clustering and vector quantization can be naturally expressed as Quadratic Unconstrained Binary Optimization (QUBO) problems. These ML applications often involve complex, high-dimensional data, which directly influences both the structure and scale of the resulting QUBO formulations. However, current quantum devices fall under the category of Noisy Intermediate-Scale Quantum (NISQ) hardware, which imposes significant limitations on qubit counts and small error rates. This dissertation investigates the impact of data complexity and data scale—as encountered in ML settings—on the effectiveness and feasibility of QO on NISQ devices. We propose novel, hardware-aware methods to overcome these challenges. The first part of this thesis focuses on the effect of data complexity for QO. We analyze how problem structure—particularly when QUBO formulations are derived from ML tasks—affects quantum solvability. We identify the spectral gap as a key factor in the success of adiabatic quantum algorithms and provide a theoretical and empirical analysis linking data-induced complexity to optimization performance.To address noise sensitivity and limited precision, we introduce a preprocessing framework based on a principled Branch-and-Bound algorithm that reduces dynamic range while preserving global optima. This improves robustness on both quantum annealers and classical solvers. In the second part, the thesis addresses challenges introduced by data scale. First, we propose a recursive Divide-and-Conquer strategy that breaks down large QUBO problems into tractable subproblems, demonstrated through an application to Bundle Adjustment in 3D scene reconstruction. Second, we introduce a variable and constraint generation method inspired by column generation for Integer Linear Programming, enabling dynamic QUBO size growth. This technique is successfully applied to Multi-Agent Pathfinding, where it scales well on NISQ devices while maintaining compatibility with classical solvers. Finally, we explore QUBO reformulations that reduce problem size through compact encodings and cyclic expansion, enabling the use of quantum hardware for tasks such as FPGA placement in chip design. Across all contributions, the developed algorithms are evaluated both theoretically and empirically, with experiments conducted on real quantum and quantum-inspired hardware. These methods significantly improve solution quality, scalability, and hardware compatibility, paving the way for more effective use of QO in practical settings. While tailored for NISQ era constraints, the results remain relevant for fault-tolerant quantum computing, offering insights into the long-term viability of QO across hardware generations.
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Rubén González Félix · QRU Quaderns de Recerca en Urbanisme · 2025
Aquest projecte s’ha dut a terme a l’equip de BCN eMotorsport amb l’objectiu de millorar la dashboard del vehicle de competición tant a nivell de software com de hardware. Pel que fa al software, s’ha implementat noves pantalles gràfiques amb TouchGFX, permetent una millor visualització de dades i navegació mitjançant l’encoder i els botons del volant. En l’ambit del hardware, s’ha substituït components obsolets com la SDRAM i la pantalla TFT per altres actuals i s’ha redissenyal la PCB per reduir-ne la mida. El sistema ara permet una monitorització més eficiente de l’estat del vehicle, facilitant la detecció d’errors sense necessitat d’un ordinador portátil.
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Santosh Pande · ACM SIGPLAN Notices · 2005
No abstract available.
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Jürgen Teich, Sandor P. Fekete · 2001
Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic reconfiguration of cells on the chip during run-time. For a given problem consisting of a set of tasks with computation requirements modeled by rectangles of cells, several optimization problems such as finding the array of minimal size to accomplish the tasks within a given time limit are considered. Existing approaches based on ILP formulations to solve these problems as multi-dimensional packing problems turn out not to be applicable for problem sizes of interest. Here, a breakthrough is achieved in solving these problems to optimality by using the new notion of packing classes. It allows a significant reduction of the search space such that problems of the above type may be solved exactly using a special branch-and-bound technique. We validate the usefulness of our method by providing computational results.
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Seda Güzel Aydın, Hasan Şakir Bılge · International Journal of Multidisciplinary Studies and Innovative Technologies · 2022
Convolutional Neural Networks (CNN) architectures have been increasingly well-known for image processing applications such as object detection, and remote sensing. Some applications like these systems need to adopt CNN methods for real-time implementation. Embedded devices like Field Programmable Gate Arrays (FPGA) technologies are a favorable alternative to implementing CNN-based algorithms. However, FPGA has some drawbacks such as limited resources and bottlenecks, it is difficult and so crucial to map the whole CNN that has a high number of layers, on FPGA without any optimization. Therefore, hardware optimization techniques are compulsory. In this study, an FPGA-based CNN architecture using high-level synthesis (HLS) is demonstrated, and a synthesis report is created for Xilinx Zynq-7000 xc7z020-clg484-1 target FPGAs. By implementing the CNN architecture on an FPGA platform, the implemented architecture has been fastened. To improve the throughput, the proposed design is optimized for convolutional layers. The most important contribution of this study is to perform optimization on the convolution layer by unrolling kernels and input feature maps and examine the effects on throughput, latency, and hardware resources. In this study, throughput is 15.6 GOP/s for the first convolution layer. With the proposed method in the study, approximately x2.6 acceleration in terms of latency and throughput was achieved compared to the baseline design.
Cited by 1Open access
Ishneet Kaur Dua, Pretesh Patel · Apress eBooks · 2024
The field of generative artificial intelligence (AI) has emerged as one of the most exciting yet computationally demanding areas within AI research today. Generative models, such as large language models, possess the remarkable ability to generate human-like text, images, video, and more, leading to a wide range of beneficial applications. However, the training and operation of these complex neural network models require immense amounts of computing power, which poses a significant challenge.
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Jürgen Teich, Sándor P. Fekete, Jörg Schepers · The Journal of Supercomputing · 2001
Cited by 46
Kristoffersson Lind, Simon, Tykesson, Johannes · Lund University Publications Student Papers (Lund University) · 2021
This thesis aims to investigate the automatic tuning of hardware parameters in a camera's image processing pipeline. In order to solve the tuning problem, it is formulated as a black-box optimization problem centered around a physical camera unit. Optimization is performed by comparing the camera's output to a reference image. Several black-box optimization algorithms were tested: Bayesian Optimization, Evolutionary Optimization, Particle Swarm Optimization, Simulated Annealing, DIRECT, and Rowan's Subplex Method. Results indicate that it is feasible to automatically tune camera hardware parameters using black-box optimization algorithms. For 14 parameters, Rowan's Subplex Method performs best with an average error of 6.25. When optimizing a much larger set of 71 parameters, Simulated Annealing, Evolutionary, and Rowan's Subplex Method perform best with an average error of 9.77, 17.92, and 18.05 respectively.
Cited by 0Open access
Santosh Pande · 2005
No abstract available.
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Pankaj K. Agarwal, Shankar Krishnan, Nabil H. Mustafa et al. · Lecture notes in computer science · 2003
Cited by 59
Kishore Noel Paul Menezes · 1997
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Putzka, J., Loebenberger, D. · MPG.PuRe (Max Planck Society) · 2009
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Leandro Santiago · 2019
Physically Unclonable Functions (PUFs) surgiram como simples primitivas de seguranca de hardware para implementar recursos de autenticacao e geracao de chaves criptograficas em dispositivos eletronicos. Um Strong PUF ideal nao e clonavel e mapeia unicamente uma entrada de n-bits para uma saida de m-bits. Contudo, implementacoes reais de Strong PUFs possuem problemas de seguranca. Esta tese propoe diversos modelos originais de Strong PUF, baseados na arquitetura de Redes Neurais sem Peso (RNP), resistentes contra ataques de construcao de modelos por meio de algoritmos de aprendizado de maquina. A fabricacao de grande volume de PUFs necessitam de tecnicas de testes online para garantir a propriedade de exclusividade entre os PUFs fabricados. Uma solucao de teste de PUF online baseado em Multi-Index Hashing (MIH) e otimizada atraves de estrategias de busca de similaridades para reduzir os recursos de memoria. Dynamic Information Flow Tracking (DIFT) tem sido utilizado com sucesso para detectar acesso ilegal a informacoes confidenciais em tempo de execucao. Nesta tese, um rastreador de fluxo implicito aninhado portatil e proposto para permitir que mecanismos baseados em fluxo explicito possam rastrear fluxos implicitos, inclusive em casos de aninhamento de lacos profundo. Alem do mais, uma nova regra de propagacao e definida para mitigar a propagacao incorreta dos dados afetados pela dependencia de controle. Enfim, novos modelos de RNP baseados em estruturas de dados probabilisticas sao propostas e analisadas com o objetivo de reduzir os requisitos de memoria. Os novos modelos sao robustos e sao adequados como componentes para solucoes de seguranca assistidas por hardware.
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F Hang · 2006
The modern core router puts forward higher and higher standards on the speed of updating table, look-up rate and capacity of look-up table.Nowadays the producer adopts the solution based on TCAMC ternary content addressable memory. The attractive ad-vantage of TCMAC goes the fast speed of look-up, and yet the updating algorithm will waste relating huge volume of storage. As to this problem, this paper presents a novel method to update the Router by using FPGA to provide the hardware supports. When in-creasing the new items, we only need to deal with the newly-increased items in advance, and it is unnecessary for forwarding table to be ordered by the length of prefix. As a result, the volume of storage reserved for the ordering of prefix is eliminated.
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Bright, Jason · ScholarWorks - UA (University of Alaska System) · 2019
Master's Project (M.S.) University of Alaska Fairbanks, 2019
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Vugts, RJHM · TU/e Research Portal (Eindhoven University of Technology) · 1992
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Soumyadip Das, Sumitra Mukhopadhyay · Applied Soft Computing · 2018
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