Mostafa Azizi · 2003
We present how Java threads are used to do concurrent coverification. The threads are scheduled with respect to the order of their priorities in the case of different priorities and by using the Round-Robin technique in the case of equal priorities. The system under coverification we are interested in consists eventually of a number of hardware and software modules described by threads at the behavioral level. The coverification process follows the execution path of the global modeled system and it verifies some specification properties during the simulation. We also discuss the case of untimed and timed coverification. An illustrative application on the broadcasting protocol of cache coherence reveals promising results.
Cited by 0
Marco Platzner · 2015
The multithreaded programming model has been shown to provide a suitable abstraction for reconfigurable computers. Previous implementations of corresponding runtime systems have been limited to a single host operating system, hard-ware platform, or application domain. This paper presents the implementation of ReconOS, our hardware/software multithreaded programming model, on both eCos and Linux-based host systems as well as on Pow-erPC and MicroBlaze CPUs. This demonstrates that Re-conOS provides a truly portable abstraction layer for pro-gramming reconfigurable computers. Further, we quantify the performance of operating system calls and measure the resulting application level performance. 1.
Cited by 0
David May · Explore Bristol Research · 2015
Cited by 0
Endrullis, Stefan · Qucosa (Saxon State and University Library Dresden) · 2008
Der Markt tragbarer Geräte gewinnt eine immer stärkere Bedeutung. Mobiltelefone, PDAs (Personal Digital Assistant), Smartphones und viele weitere Geräte werden kontinuierlich mit neuen Funktionen ausgestattet und übernehmen zunehmend klassische Aufgaben eines Personal Computers (PC), wie beispielsweise die Textverarbeitung oder die Ausführung multimedialer Anwendungen. Speziell letztere stellen an die Geräte hohe Anforderungen, die sich nicht allein durch den Einsatz leistungsstärkerer Prozessoren lösen lassen. Nicht selten werden deshalb für rechenaufwendige Arbeiten Chips zur Umsetzung der speziellen Anforderungen in Hardware eingesetzt. Diese werden als Application Specific Integrated Circuit (ASIC) bezeichnet.
Cited by 0Open access
David G. Márquez, Adrián Cristal Kestelman, Esteban Mocskos · IEEE Computer Architecture Letters · 2016
Multi-core processors are ubiquitous in all market segments from embedded to high performance computing, but only few applications can efficiently utilize them. Existing parallel frameworks aim to support thread-level parallelism in applications, but the imposed overhead prevents their usage for small problem instances. This work presents Micro-threads (Mth) a hardware-software proposal focused on a shared thread management model enabling the use of parallel resources in applications that have small chunks of parallel code or small problem inputs by a combination of software and hardware: delegation of the resource control to the application, an improved mechanism to store and fill processor's context, and an efficient synchronization system. Four sample applications are used to test our proposal: HSL filter (trivially parallel), FFT Radix2 (recursive algorithm), LU decomposition (barrier every cycle) and Dantzig algorithm (graph based, matrix manipulation). The results encourage the use of Mth and could smooth the use of multiple cores for applications that currently can not take advantage of the proliferation of the available parallel resources in each chip.
Cited by 1
Gonzalez Marquez, David Alejandro, Kestelman, Adrian Cristal, Mocskos, Esteban Eduardo · Conicet · 2017
Multi-core processors are ubiquitous in all market segments from embedded to high performance computing, but only few applications can efficiently utilize them. Existing parallel frameworks aim to support thread-level parallelism in applications, but the imposed overhead prevents their usage for small problem instances. This work presents Micro-threads (Mth) a hardware-software proposal focused on a shared thread management model enabling the use of parallel resources in applications that have small chunks of parallel code or small problem inputs by a combination of software and hardware: Delegation of the resource control to the application, an improved mechanism to store and fill processor's context, and an efficient synchronization system. Four sample applications are used to test our proposal: HSL filter (trivially parallel), FFT Radix2 (recursive algorithm), LU decomposition (barrier every cycle) and Dantzig algorithm (graph based, matrix manipulation). The results encourage the use of Mth and could smooth the use of multiple cores for applications that currently can not take advantage of the proliferation of the available parallel resources in each chip.
Cited by 0Open access
Nicolas Estibals, Gaël Deest, Ali El-Moussawi et al. · HAL (Le Centre pour la Communication Scientifique Directe) · 2016
International audience
Cited by 0
Rahul Sharma, Yamuna Rajasekhar, Ron Sass · 2012
Fine-grain thread parallelism using task based programming models are a new trend in achieving massively parallel computations. Often, software pre-fetching and queuing mechanisms for managing these dynamic environments are inadequate, failing to keep the processor cores busy with computation. At the same time, the CPU-memory performance gap is getting worse and this puts a strain on memory subsystem to keep cores in a busy state. We describe a hardware based pre-fetching and queuing mechanism aimed at assisting the over-subscription of very lightweight threads per core. Experiments with a soft processor and a reconfigurable accelerator core are reported. The hardware demonstrates the ability to block on out-of-order memory transactions and alleviates the software bottleneck.
Cited by 2
Xinyu Feng, Zhong Shao, Yuan Dong et al. · 2008
Hardware interrupts are widely used in the world's critical software systems to support preemptive threads, device drivers, operating system kernels, and hypervisors. Handling interrupts properly is an essential component of low-level system programming. Unfortunately, interrupts are also extremely hard to reason about: they dramatically alter the program control flow and complicate the invariants in low-level concurrent code (e.g., implementation of synchronization primitives). Existing formal verification techniques---including Hoare logic, typed assembly language, concurrent separation logic, and the assume-guarantee method---have consistently ignored the issues of interrupts; this severely limits the applicability and power of today's program verification systems.
Cited by 79
Prerna Budhkar, Ildar Absalyamov, Vasileios Zois et al. · ACM Transactions on Architecture and Code Optimization · 2019
Inexpensive DRAMs have created new opportunities for in-memory data analytics. However, the major bottleneck in such systems is high memory access latency. Traditionally, this problem is solved with large cache hierarchies that only benefit regular applications. Alternatively, many data-intensive applications exhibit irregular behavior. Hardware multithreading can better cope with high latency seen in such applications. This article implements a multithreaded prototype (MTP) on FPGAs for the relational selection operator that exhibits control flow irregularity. On a standard TPC-H query evaluation, MTP achieves a bandwidth utilization of 83%, while the CPU and the GPU implementations achieve 61% and 64%, respectively. Besides being bandwidth efficient, MTP is also 14.2× and 4.2× more power efficient than CPU and GPU, respectively.
Cited by 3Open access
Xinyu Feng, Zhong Shao, Yu Guo et al. · Journal of Automated Reasoning · 2009
Cited by 42
Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan et al. · ACM Transactions on Architecture and Code Optimization · 2008
Thread-level speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. In this article, we focus on one important limitation of program performance under TLS, which stalls as a result of synchronizing and forwarding scalar values between speculative threads that would otherwise cause frequent data dependences and, hence, failed speculation. Using SPECint benchmarks that have been automatically transformed by our compiler to exploit TLS, we present, evaluate in detail, and compare both compiler and hardware techniques for improving the communication of scalar values. We find that through our dataflow algorithms for three increasingly aggressive instruction scheduling techniques, the compiler can drastically reduce the critical forwarding path introduced by the synchronization and forwarding of scalar values. We also show that hardware techniques for reducing synchronization can be complementary to compiler scheduling, but that the additional performance benefits are minimal and are generally not worth the cost.
Cited by 26Open access
Wentong Li · 2007
With the advances in very large scale integration (VLSI) technology, hundreds of billions of transistors can be packed into a single chip. With the increased hardware budget, how to take advantage of available hardware resources becomes an important research area. Some researchers have shifted from control flow Von-Neumann architecture back to dataflow architecture again in order to explore scalable architectures leading to multi-core systems with several hundreds of processing elements. In this dissertation, I address how the performance of modern processing systems can be improved, while attempting to reduce hardware complexity and energy consumptions. My research described here tackles both central processing unit (CPU) performance and memory subsystem performance. More specifically I will describe my research related to the design of an innovative decoupled multithreaded architecture that can be used in multi-core processor implementations. I also address how memory management functions can be off-loaded from processing pipelines to further improve system performance and eliminate cache pollution caused by runtime management functions.
Cited by 0Open access
Salamanca Guillén, Juan Jesús, 1988- · LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) · 2016
Cited by 0Open access
Andrzej Pułka, Ernest Antolak, Bartłomiej Truś · International Journal of Applied Mathematics and Computer Science · 2026
This paper presents and tests several task scheduling methods in a real-time multitasking system based on the thread interleaving mechanism. The original configurable multicore time-predictable system architecture for multitasking is briefly discussed. The essential requirement of the system is the predictability of tasks, regardless of their number and when they are initialized. The paper focuses on the appropriate configuration of core interleaving registers, which determine the order and frequency of execution of individual tasks. This study develops various heuristic algorithms based on genetic programming and task execution rate analysis, and implements these in the Python language and PROLOG. The experiments are conducted with different task scenarios and system work requirements: with minimization of resources, energy, and operating frequency. A special task analyzer is used to evaluate the quality of the resulting system configuration. The results obtained are tested on a real hardware structure implemented in an FPGA chip. The proposed approach can be a useful tool for configuring real-time multitasking systems.
Cited by 0Open access
Jeronimo Costa Penha, Lucas Bragança da Silva, Michael Canesche et al. · 2022
O uso de aceleradores com paralelismo espacial, como os CGRAs, são soluções promissoras em desempenho e eficiência energética. O desempenho dos CGRAs dependem dos compiladores para explorar o paralelismo das aplicações, sendo o mapeamento da aplicação um dos grandes desafios. A primeira etapa deste processo é o posicionamento, cuja eficiência impacta diretamente nos passos seguintes que são o roteamento e o escalonamento. Este trabalho apresenta uma implementação em hardware, usando field-programmable gate arrays (FPGA), para o algoritmo Simulated Annealing (SA). Os resultados mostram uma aceleração de 7 a 30 vezes em relação ao estado da arte sem sacrificar a qualidade da solução, podendo ser de 70 a 300 vezes mais rápido com o uso de múltiplas unidades de posicionamento. O algoritmo foi implementado em pipeline com múltiplas threads para esconder a latência, onde uma iteração completa do SA executa em apenas dois ciclos de relógio do FPGA.
Cited by 0Open access
Dipl.-Ing. Marko Rößler · 2013
Cited by 0
Rößler, Marko · Qucosa - Monarch (Chemnitz University of Technology) · 2013
Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous computing resources such as programmable processors units (CPU’s or DSP’s) and highly specialized hardware cores. These platforms have been scaled down to integrated embedded system-on-chip. Modern platform FPGAs enhance such systems by the flexibility of runtime configurable silicon. One of the major advantages that arises is the ability to use hardware (HW) and software (SW) resources in a time-shared manner. Though the ability to dynamically assign computing resources based on decisions taken at runtime is given.
Cited by 0Open access
Marko Chair, D Andrews, R Sass et al. · State and University Library Dresden (Saxon State Library) · 2013
Cited by 0Open access
Manoj Gupta, Fermín Sánchez Carracedo, Josep Llosa · 2009
Several multithreading techniques have been proposed to reduce the resource underutilization in very long instruction word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique which improves processor performance by issuing multiple instructions from different threads. SMT requires extra hardware to merge instructions from different threads. The complexity of this hardware increases substantially with the number of threads, limiting the number of threads that can be realistically supported to only 2. Cluster-level Simultaneous MultiThreading (CSMT) is a technique that merges instructions from threads at the cluster level. CSMT has a much lower merging hardware cost and can support a larger number of threads. However, CSMT performance is lower than SMT. In this paper, we evaluate several hardware designs that can support a high number of threads by using a merging scheme that combines both SMT and CSMT merging. For instance, one of the evaluated schemes, which merges the first 2 threads using SMT and the produced merging with other 2 threads by CSMT, achieves performance similar to supporting 4 threads by SMT but maintaining a reasonable merging hardware cost.
Cited by 0