Hiroyuki Sugita, Võ Quang Minh, T. Masuzaki et al. · 2004
An efficient scheme for JPEG2000 progressive decoding is proposed, which is capable of handling image codestreams with SNR progressiveness. In order to avoid processing the same codestream data more than once when decoding SNR progressive images, a pair of techniques are introduced in our decoding scheme; reusing of intermediary decoded data and differential IDWT. Comprehensive evaluation of our scheme demonstrating that with 20% increase of required memory size, more than 40% of computational costs can be reduced in comparison with conventional (non-progressive) decoding scheme.
Cited by 0
John Snyder · 1983
Cited by 15
R. T. Chien · IEEE Transactions on Information Theory · 1969
This paper describes a technique for high-speed decoding of burst-error-correcting codes and a class of codes most suitable for this purpose. With a small amount of additional circuitry the decoders proposed in this paper are capable of decoding speeds several orders of magnitude higher than those of conventional decoders.
Cited by 44
Mikael Karlsson Rudberg, Lars Wanhammar · 1997
This paper introduces a new class of Huffman decoders which is a developmet of the parallel Huffman decoder model. With pipelining and partitioning, a regular architecture with an arbitrary degree of pipelining is developed. The proposed architecture dramatically reduces the symbol decoder requirements compared to previous results, and still is the actual implementation of the symbol decoder not treated. The proposed architectures also have a potential of realizing high speed, low power Huffman decoders. 1.
Cited by 0
Taeseok Kang, Doyeon Lim, Wonjin Lee et al. · ACS Nano · 2026
DNA-based storage offers exceptional information density, durability, and energy efficiency compared to conventional digital media, yet practical implementation faces challenges including high synthesis costs, sequencing errors, and slow access speeds. Here, we present an integrated DNA storage system with optimized encoding and processing strategies to address practical implementation issues. Our approach achieves 9.78 bits/nt net information density with a flexible index allocation system handling data volume from 0.37 KB to 2.79 × 10<sup>22</sup> YB. The decoding process delivers 360× faster throughput than traditional methods, processing 4.57 million reads (1.63 GB) in 34.5 s and demonstrating perfect data retrieval from down-sampled (×5.33) sequencing in 2.47 s. Our error correction system combines inner Reed-Solomon with outer XOR code, ensuring reliable recovery with large reading sequences (92,626) and low copy number data (×0.52). The streamlined NGS preparation workflow reduces processing time from ∼4.5 to ∼2 h while decreasing per-sample costs from ∼$60 to ∼$0.50. The system demonstrates versatility through high-fidelity DNA data storage ink and implementations ranging from physical stamps to VR platforms. This technology establishes a foundation for practical DNA data storage solutions applicable to cultural heritage preservation, autonomous vehicle data management, and matrix-based machine learning applications.
Cited by 0
Vincent Pignoly, Bertr Le Gal, Christophe Jégo et al. · 2020
In this paper, an architecture to implement horizontal layered Gallager E is proposed to decode QC-LDPC codes onto Field-Programmable Gate Array (FPGA). It arises as an attractive solution for wireless optical up-link space communication because of its low hardware complexity considering constraints in space. Very high throughput of several Gpbs is aimed. Moreover, at this bit rate, space systems imply hard inputs for the decoding process. Gallager E implementation represents an efficient trade-off between throughput, error correction capability and computational complexity. More than 1.5 Gbps are reached by the proposed decoders onto a Xilinx space-grade FPGA. One can note that higher throughput (3 Gbps) can be achieved on other recent FPGAs with increased working frequency.
Cited by 2
Duk Gun Choi, Jin Hee Jeong, Min Gyu Kim et al. · 2006
In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improved the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times
Cited by 1
Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2002
Turbo decoders inherently have large decoding latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high-speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, the segmented sliding window approach and two other types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units, and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. To reduce the storage bottleneck for each subdecoder, a modified version of the partial storage of state metrics approach is presented. The new approach achieves a better tradeoff between storage part and recomputation part in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes do not cause performance degradation.
Cited by 62
Defeng Ren, Jianhua Ge, Jing Li · Wireless Personal Communications · 2011
Cited by 9
Dino A. Gianisis, John S. Prince, John J. Kwiat · 1985
This paper examines the use of digital GaAs IC's in the receiver portion of a bus interface unit (BIU) that is being developed to connect to an electrical high-speed data bus (HSDB). The receiver includes a GaAs Manchester decoder and 100K ECL circuits for serial to parallel data conversion. The decoder consists of a 300 equivalent gate, GaAs cell array along with standard MSI digital GaAs D-MESFET IC's (four-bit universal shift register, divide by 2/4/8 binary counter). The GaAs chip set decodes 100 Mbit/s Manchester II encoded data. The cell array has been designed and fabricated. Functional testing of the cell array has shown working parts on the first iteration with a 20% yield. Incoming asynchronous Manchester II data is oversampled and processed using a 1.25 ns cycle time. The cell array outputs differential NRZ data and clock along with an error detect bit.
Cited by 1
Gerhard Fettweis, H. Meyr · IEEE Communications Magazine · 1991
The Viterbi algorithm (VA) is considered as an example of a fairly complex algorithm that needs to be implemented for high-speed applications. A brief introduction to the algorithm is given, and the state of the art of high-speed Viterbi decoders is reviewed. The three principal levels of introducing additional parallelism into an algorithm-bit level, word level, and algorithm level-are outlined, and a solution for the VA at the bit level is indicated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 156
Moulay Seddiq El Kasmi Alaoui, Saïd Nouh, Abdelaziz Marzak · International journal of intelligent engineering and systems · 2018
Digital transmission systems carry information from the source to the receiver using a physical medium such as cable, fiber optic or even propagation on a radio channel which isn't entirely reliable and causes the change of data originally emitted. Today the use of error correcting codes for protection and correction becomes an integral part in the design of communication systems and computers. In this work, we present a new interesting way to accelerate the decoding process of linear codes. The proposed method called Soft Decision Decoder by Hash Techniques (SDHT) is based on syndrome-decoding algorithm and hash techniques. The use of this latest allows reducing considerably the search time of all possible error patterns of weights less than a fixed threshold. SDHT is applicable on many linear codes and exploit the polynomial form to reduce again the run time decoding for cyclic codes. SDHT is successfully applied to decode some Bose Ray-Chaudhuri and Hocquenghem (BCH), Quadratic Residue (QR) and Extended Quadratic Residue (EQR) codes. The simulation results show that the proposed SDHT yield to good error correcting performances with reduced complexity. The comparison between SDHT and many competitors shows that it gives better performances in terms of correction rate. The experimental study of the decoding steps for the BCH(63,45,7) code shows that the time search of the most likely error pattern is reduced at about 26214153% comparing to an exhaustive search of all possible error patterns of weights less than or equal to 4. This study proves the huge success of the proposed SDHT decoder.
Cited by 7Open access
G.D. Bergman · Microprocessors and Microsystems · 1987
Cited by 2
Ke-xiang MA, Ji-cheng SUN, Meng WANG et al. · SHILAP Revista de lepidopterología · 2014
In order to improve the decoding speed of the RRWBF algorithm, a multiple-bits selection mechanism was proposed to accelerate the decoding convergence speed of the RRWBF algorithm. However, the RRWBF algorithm with the multiple-bits selection mechanism will appear the bit-repeated flipping, which can impair the decoding performance of the RRWBF algorithm. Hence, a bit-repeated flipping elimination mechanism was proposed to reduce the bit-repeated flipping in the process of the multiple-bits flipping decoding. Simulation results show that the RRWBF algorithm with the multiple-bits selection and the repeated flipping elimination mechanism has a much faster decoding speed at the cost of a little decoding performance loss compared with the RRWBF algorithm.
Cited by 0Open access
S. Palanivel Rajan, M. Paramaiyappan · 2025
Soft-decision decoding plays a crucial role in achieving near-capacity error correction performance for modern communication standards such as 5G and 6G. However, existing soft-decision decoders often suffer from high complexity, large area overhead, and limited throughput, making them less suitable for high-speed applications. This paper proposes a high-throughput VLSI architecture for soft-decision decoding based on the Ordered Reliability Bits Guessing Random Additive Noise Decoding (ORBGRAND) algorithm. The novelty of the proposed approach lies in its pipelined and parallelized noise-guessing engine, lightweight reliability sorting mechanism, and optimized memory hierarchy, which collectively minimize latency and improve energy efficiency. The overall methodology involves algorithmic optimization, architecture design in HDL, simulation under AWGN channels, FPGA synthesis, and benchmarking against existing GRAND-based decoders. Experimental results demonstrate that the proposed architecture achieves multi -Gbps throughput, lower decoding latency, and superior error-correction performance with reduced area and power consumption. These results highlight its potential as an efficient solution for next-generation high-speed communication systems.
Cited by 0
Qingming Huang, Wei Lin, Liao Teng · 2009
Change original PNG software decode, update decode algorithm, implement hardware Huffman decoder, speed up PNG decode process. This paper discuss the implementation of Huffman decoder in ASIC based on the feature of table and compressed data. The result under the test of EDA tools and Matlab shows the Huffman decoder for PNG decode without distortion.
Cited by 0
Bruno Bougard, Alexandre Giulietti, Claude Desset et al. · 2003
Cited by 6
Uehara, Gregory T., Lin, Shu · NASA Technical Reports Server (NASA)
In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.
Cited by 0Open access
Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi · 2002
Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes introduce no performance degradation in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented.
Cited by 10
Shankar Balasubramanian · Angewandte Chemie International Edition · 2011
At warp speed: The speed and cost of sequencing DNA has undergone tremendous improvement based on Solexa sequencing. This technique arose from basic curiosity-driven research and unexpected outcomes, rather than from ideas that were strategically driven. The whole-genome sequencing of individuals now possible may one day transform the way medical disorders are classified, diagnosed, and treated.
Cited by 15