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About 10,000 papers for “loop optimization”

Tip-Tilt Control Loop Optimization

L. Fini, Simone Esposito · Adaptive Optics · 1996

We address problems of control loop parameters optimization for tip-tilt correction system based on the approach followed for the T.N.G. tracking system.

Cited by 0

DOPPLER TRACKING LOOP OPTIMIZATION STUDY

Defense Technical Information Center (DTIC) · 1962

The purpose of this study was to investigate methods for improving the performance of the phase-locked loop receiver, particularly as a reliable means for locking onto, and determining precisely, the doppler frequency shift of a 2-gc carrier in the presence of noise. The following subjects are discussed in detail: adaptive phase-lock theory, receiver description, optimization of phase-locked loop lock-on, interference to a tracking loop from an unwanted carrier (with limiting), and doppler loop threshold

Cited by 0

SNAP-8 third loop optimization

Cleveland, F. R., Rico, L., Perez, E. F. · NASA STI Repository (National Aeronautics and Space Administration)

Eutectic sodium potassium and OS-124 considered as coolant fluids for SNAP-8 third loop - optimum loop operating parameters

Cited by 0

Memory requirement optimization with loop fusion and loop shifting

Qubo Hu, M. Palkovic, Per Gunnar Kjeldsberg · 2004

Loop fusion and loop shifting are well recognized loop transformations for memory requirement reduction. State-of-the-art optimizations with loop fusion and shifting are based on heuristics without any evaluation of the resulting effects during each optimization step. Thus we cannot guarantee that each step results in a reduced overall memory requirement. On the other hand, most memory requirement estimations at system level are inefficient and slow. Also the estimation is not started until the optimization is done. Having to iterate between optimization and estimation is very time consuming. In this paper, we present a storage requirement optimization method which combines the optimization and estimation processes with the goal to have continuous estimates during the optimization and hence to achieve lower memory requirements.

Cited by 1

Continual Human-in-the-Loop Optimization

Liao, Yi-Chi, Streli, Paul, Li, Zhipeng et al. · Repository for Publications and Research Data (ETH Zurich) · 2025

Optimal input settings vary across users due to differences in motor abilities and personal preferences, which are typically addressed by manual tuning or calibration. Although human-in-the-loop optimization has the potential to identify optimal settings during use, it is rarely applied due to its long optimization process. A more efficient approach would continually leverage data from previous users to accelerate optimization, exploiting shared traits while adapting to individual characteristics. We introduce the concept of Continual Human-in-the-Loop Optimization and a Bayesian optimization-based method that leverages a Bayesian-neural-network surrogate model to capture population-level characteristics while adapting to new users. We propose a generative replay strategy to mitigate catastrophic forgetting. We demonstrate our method by optimizing virtual reality keyboard parameters for text entry using direct touch, showing reduced adaptation times with a growing user base. Our method opens the door for next-generation personalized input systems that improve with accumulated experience.

Cited by 0Open access

Nested Loop Optimization on the TMS320C6x

Richard Scales · 1999

This document descibes the process used to develop and optimize nested loops for the Texas Instruments (TIa) TMS320C6x digital signal processor (DSP). The performance of loops can greatly affect the performance of entire applications. Many loops are nested loops with both an inner and outer loop. To optimize nested loops it is necessary to consider both the inner loop and the outer loop performance, especially when the inner loop count is small for execution of each outer loop. Design Problem In many typical DSP applications, loops comprise a majority of the number of cycles, or MIPS. Because of this, performance of loops can greatly affect the performance of the entire application. Many of these loops are nested loops with both an inner and outer loop. Some common examples are FIR and IIR filters, FFT, and DCT. To optimize these nested loops, it is necessary to consider not only the inner loop performance but also the outer loop performance, especially when the inner loop count is small for execution of each outer loop. One technique used to optimize loops on the highly parallel C6x VelociTI architecture is software pipelining. This involves initiating new iterations of the loop before previous iterations have completed to obtain high throughput. This implies there are some cycles (loop prolog) to begin executing, or pipe up, of each inner loop and some more cycles to pipe down the loop (loop epilog). These cycles will be incurred for each outer loop execution so they can affect performance, especially when the inner loop count is small. The more deeply pipelined the DSP is, the more cycles will be required for the prolog and epilog. Figure 1 shows a simple dot product example, (with non-C6x-like single cycle loads and multiplies), where inner loop setup is 2 cycles, the prolog is 2 cycles, the epilog is 2 cycles, and the time to execute outer loop instructions is 2 cycles. At the end of cycle 9 there is a branch back to the beginning of the loop setup (Br 1). Thus, 8 cycles will be incurred each time this inner loop is executed in an outer loop. As we move to deeper and deeper pipelines in DSPs for higher clock speeds, the number of cycles of overhead will increase. The higher the number of cycles for setup, prolog, epilog, and outer loop instructions, and the lower the inner loop count, the more overall nested loop performance is reduced. Application Report SPRA519 Nested Loop Optimization on the TMS320C6x 2 Figure 1. Nested Loop w/ Software Pipelined Inner Loop

Cited by 9

Closed Loop Identification by Optimization Method

Valeriy F. Dyadik, Nikolay Krinitsyn, Vyacheslav A. Rudnev · Advanced materials research · 2015

The article is devoted to the adaptation of the controller parameters during its operation as a part of a control loop. The possibility to identify the parameters of the controlled plant model in the closed control loop has been proved by a computer simulation. The described active identification method is based on the response processing of the closed loop control system to standard actions. The developed algorithm has been applied to determine the model parameters of the flaming fluorination reactor used for the production of uranium hexafluoride. Designed identification method improves the quality of the product and the efficiency of the entire production.

Cited by 0

Loop alignment for memory access optimization

Antoine Fraboulet, Guillaume Huard, Anne Mignotte · 1999

Portable or embedded systems allow more and more complex applications like multimedia today. These appli-cations and submicronic technologies have made the power consumption criterium crucial. We propose new techniques thanks to which we can optimize the behavioral description of an integrated system before the hardware/software par-titioning (Codesign). These transformations are performed on “for ” loops that constitute the main parts of the multime-dia code which handle the arrays. We present in this paper two new (polynomial) techniques for minimizing memory accesses in loop nests by data temporal locality optimiza-tion. 1

Cited by 0

Human-in-the-loop Bayesian optimization.

Myunghee Kim (695702), Ye Ding (40594), Philippe Malcolm (281731) et al. · Figshare · 2017

<p>The metabolic cost was estimated using 40 breaths of respiratory data (approximately two minutes altogether) at a step frequency prescribed via metronome. Using the measured step frequency and the estimated metabolic cost, the algorithm computed a posterior distribution of metabolic cost as function of the step frequency. The resulting distribution was used with the expected improvement metric to select the next step frequency.</p>

Cited by 0Open access

Optimization of Nest-Loop Software Pipelining

Qingfeng Zhuge, Zili Shao, Edwin H. -m. Sha · 2014

Embedded systems have strict timing and code size requirements. Software pipelining is one of the most important optimization techniques to improve the execution time of loops by increasing the parallelism among successive loop iterations. However, little research has been done for the software pipelining problem on nested loops. The existing software pipelining techniques for single loops can only explore the innermost loop parallelism of a nested loop, so the final timing performance is inferior. While multi-dimensional (MD) retiming can explore the outer loop parallelism, it introduces large overheads in loop index generation and code size due to transformation. In this paper, we propose theory and algorithms of software pipelining for nested loops with minimal overheads based on the fundamental understanding of the properties of software pipelining for nested loops. We show the relationship among execution sequence, execution time of loop body, and software pipelining degree of a nested loop using retiming concepts. Two algorithms of Software PIpelining for NEsted loops (SPINE) are proposed: The SPINE-FULL algorithm generates fully parallelized loops with computation and code size overheads as small as possible. The SPINE-ROW-WISE algorithm generates the best possible parallelized loops with the minimal overheads. Our technique can be directly applied to imperfect nested loops. The experimental results show that the average improvement on the execution time of the pipelined loop generated by SPINE is 71.7 % compared with that generated by the standard software pipelining approach. The average code size is reduced by 69.5 % compared with that generated by MD retiming.

Cited by 0

Energy Optimization on OpenMP Loop Scheduling

Yong Dong, Juan Chen · Journal of Software · 2012

Energy consumption has become a serious problem in high-performance computing (HPC) systems. Parallel loops often occupy a significant part of the execution time of overall parallel programs. Thus, reducing their energy consumption is the key to the reduction in energy consumption of the program. This paper discusses energy optimization in OpenMP loop scheduling, which is a method of optimizing energy consumption of parallel loops within a certain performance loss. OpenMP programming includes Uniform-Sized scheduling unit (US)-based Energy-saving Optimal Static Scheduling algorithm (EOSS), UnUniform-Sized scheduling unit (UUS)-based Energy-oriented Static Scheduling algorithm (ESS). EOSS obtains the maximum energy savings under the ideal condition (US) by combining loop rescheduling and voltage/frequency scaling. ESS optimizes energy consumption under the non-ideal condition (UUS). We evaluate these energy-oriented loop scheduling algorithms through simulations on a multiprocessor system. Taking 160 processors as example, five NPB programs with EOSS can reduce 43.5% energy consumption on the average, which is 2.1% more energy saved than the DVFS-only method. ESS can achieve 54% energy savings with the example code we use.

Cited by 1

Loop Optimization for Tensor Network Renormalization

Shuo Yang, Zheng‐Cheng Gu, Xiao-Gang Wen · Physical Review Letters · 2017

We introduce a tensor renormalization group scheme for coarse graining a two-dimensional tensor network that can be successfully applied to both classical and quantum systems on and off criticality. The key innovation in our scheme is to deform a 2D tensor network into small loops and then optimize the tensors on each loop. In this way, we remove short-range entanglement at each iteration step and significantly improve the accuracy and stability of the renormalization flow. We demonstrate our algorithm in the classical Ising model and a frustrated 2D quantum model.

Cited by 163Open access