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About 589 papers for “multi-thread programming”

Implementation of Lock-Free shared_ptr and weak_ptr for C++11 multi-thread programming

TaeKyun Ku, NaiHoon Jung · Journal of Korea Game Society · 2021

고성능이 요구되는 게임 프로그래밍에서 멀티스레드 프로그래밍은 필수이다. 하지만 널리 사용되는 C++11의 shared_ptr와 weak_ptr는 멀티스레드 환경에서 오작동 및 성능 문제를 가지고 있다. 본 논문에서는 기존의 오작동 방지 방법보다 높은 성능을 가지는 Lock-Free shared_ptr와 weak_ptr를 제안한다. 제안하는 두 객체는 논블로킹 알고리즘을 이용하여 멀티스레드에서의 데이터 레이스를 방지하였으며, 8스레드 환경에서 실험한 결과 스레드 사이의 경쟁이 낮은 상황에서 기존의 방법보다 최대 7424% 향상되었고, 경쟁이 높은 상황에서 최대 3767% 향상된 성능을 보여준다.

Cited by 0

A new approach for software-simulation of membrane systems using a multi-thread programming model

Daniel Cascado-Caballero, Fernando Díaz-del-Río, Daniel Cagigas-Muñiz et al. · Simulation Modelling Practice and Theory · 2024

The evolution of simulation and implementation of P systems has been intense since the theoretical model of computation was created. In the field of software simulation of P systems, the proposals made so far have taken advantage mainly of the parallelism of GPUs, but not of the parallelism of existing multi-core processors. This paper proposes a new model for simulating P systems using a multi-threaded approach in a multi-core processor. This simulation approach establishes a new paradigm that is entirely in line with the philosophy of P-systems: since objects must react in parallel, asynchronously and autonomously with other objects, simulation using multiple synchronized threads completely mimics the behavior of objects within a membrane. This proposal has been implemented and tested using a simulator programmed in C#, and its correct operation has been tested for confluent and non-confluent systems. The experimental results confirm that the simulator scales well with the number of hardware threads of a multiprocessor. The obtained results show that the new model is correct and that it can be extended to other more complex types of P systems, in order to discover which are the limit of this multi-threaded approach when running it in multi-core processors. • A pioneering approach for membrane simulation based on CPU multi-threading. • The approach can be straightforwardly used to simulate generic transitive P systems. • A multi-threaded implementation of the P system simulator has been tested. • Performance speedup results directly proportional to the number of hardware threads.

Cited by 1Open access

Real-Time Virtual Instrument Platform Based on Multi-Thread Technique

Meng Lun Tao, Ding Fang Chen, Quan Guo Lu et al. · Advanced materials research · 2012

In Virtual instrument (VI) established for computer based automated test and control, the process with only single thread has limits when developed for acquiring high speed data, analyzing and displaying them the meaning while. Any interference from another task may block the whole running process and cause data missing. In order to increase the throughput, responding time and multi-task processing efficiency of VI, multi-thread programming with the platform LabWindows/CVI is introduced in this paper. Contents include the two strategies to establish multi-thread program, Thread pool and Asynchronous Timer, and how to protect data with multi-thread programming. Finally, a case study showed a multi-thread VI based on Asynchronous Timer method, with the comparison of performance between single thread and multi-thread program.

Cited by 1

Global EDF Schedulability Analysis for Synchronous Parallel Tasks on Multicore Platforms

Hoon Sung Chwa, Jinkyu Lee, Kieu-My Phan et al. · 2013

The trend towards multi-core/many-core architectures is well underway. It is therefore becoming very important to develop software in ways that take advantage of such parallel architectures. This particularly entails a shift in programming paradigms towards fine-grained, thread-parallel computing. Many parallel programming models have been introduced targeting such intra-task thread-level parallelism. However, most successful results on traditional multi-core real-time scheduling are focused on sequential programming models. For example, thread-level parallelism is not properly captured into the concept of interference, which is key to many schedulability analysis techniques. Thereby, most interference-based analysis techniques are not directly applicable to parallel programming models. Motivated by this, we extend the notion of interference to capture thread-level parallelism more accurately. We then leverage the proposed notion of parallelism-aware interference to derive efficient EDF schedulability tests that are directly applicable to synchronous parallel task models on multi-core platforms. Our evaluation results indicate that the proposed analysis significantly advances the state-of-the-art in EDF schedulability analysis for synchronous parallel tasks.

Cited by 63

Parallel Beam Search Algorithms for Domain-Independent Dynamic Programming

Ryo Kuroiwa, J. Christopher Beck · Proceedings of the AAAI Conference on Artificial Intelligence · 2024

Domain-independent dynamic programming (DIDP), a model-based paradigm based on dynamic programming, has shown promising performance on multiple combinatorial optimization problems compared with mixed integer programming (MIP) and constraint programming (CP). The current DIDP solvers are based on heuristic search, and the state-of-the-art solver, complete anytime beam search (CABS), uses beam search. However, the current DIDP solvers cannot utilize multiple threads, unlike state-of-the-art MIP and CP solvers. In this paper, we propose three parallel beam search algorithms and develop multi-thread implementations of CABS. With 32 threads, our multi-thread DIDP solvers achieve 9 to 39 times speedup on average and significant performance improvement over the sequential solver, finding the new best solutions for two instances of the traveling salesperson problem with time windows. In addition, our solvers outperform multi-thread MIP and CP solvers in four of the six combinatorial optimization problems evaluated.

Cited by 2Open access

Multi-thread based synchronization of locomotion control in snake robots

Laxmisha Rai, Soon Ju Kang · 2005

In this paper, we present an approach to control the locomotion of snake robot with concurrent programming model constructed using threads and semaphores. The multi-thread based concurrent programming model adds the flexibility to design and synchronize the movement of snake robots as compared with microcontroller and mechanical based approaches. We have designed a physical snake robot using LEGO sensors and actuator blocks and the wave motion of the snake robot is generated by multi-thread based concurrent programming under RT-Linux. The different robot movements in a desired direction along with different types of snake movements are achieved using angle sensors.

Cited by 20

Research on Full-Chip Programming for Sunway Heterogeneous Many-core Processor

Wei Wu, Hong Qian, Qi Zhu et al. · 2021

Programming on many-core processors is a challenging task. It's a difficult topic to program and compile on heterogeneous many-core architectures in high-performance computing area. The bottom-level programming support on Sunway many-core processors is insufficient and can hardly satisfy the growing need in applications. This paper conducts an thread accelerated programming model and a multi-mode accelerating thread library on Sunway architectures. A fast thread group mode is proposed, which can reduce the consumption of thread spawn and join according to hardware's features. Compared to GPU, it achieves a speedup of 24.88. We also designs a globally sharing executing mode, which supports many-core acceleration programming from the view of full-chip. Evaluation results on the Parboil benchmark shows that, the average performance is 1.16 times as NVIDIA V100 GPU.

Cited by 1

A Parallel Computing Component for Linux Cluster with Threads Binding Supports

Hang Zhou, Ximin Wang, Yinghua Guo · 2010

A hybrid MPI+OpenMP programming mode can achieves high performance advantage over pure MPI for the application on SMP cluster because of the multi cores architecture. However, code development can be extremely difficult for the multi-granularity parallelism programming. This paper presents a reusable component model to make the programming become ease. The proposed component encapsulates a SPMD program that run as a process on SMP processors in a data parallel manner. The component provides a thread setting interface. By the interface, the component can be partitioned into multi fine-granularity threads and the threads can be running on multi core of a SMP processor. In order to avoiding the migrating of threads from one core to another frequently due to the scheduling of Linux, a thread binding interface of the component is also defined based on OpenMP facilities. With the interface, a thread in a component can be bind to core. As an example, the component model is used for FFT application based on a Linux server with an Intel Xeon E5506 processor. The experiments indicate that the component with thread binding supports can be used for high performance parallel computing applications.

Cited by 3

A Light-Weight Cooperative Multi-threading with Hardware Supported Thread-Management on an Embedded Multi-Processor System

Bo‐Cheng Lai, Patrick Schaumont, Ingrid Verbauwhede · 2006

paper proposes a light-weight cooperative multi- threading programming model for an embedded multi- processor system. The synchronization between different threads is obtained by a test-and-set-lock. Each processor needs to acquire the lock before accessing shared resources. To reduce the overhead of software thread-management, a hardware thread-queue manager is added to maintain the stack pointer for each thread. This reduces off-chip memory accesses during context switches. The whole multi-processor system, including software stack and hardware architecture, is evaluated with a cycle-accurate simulation platform. With a data-flow-based image encoder as the driver application, the multi-processor system with hardware thread-queue manager achieves 9.5% performance speedup compared to a pure software thread-queue manager.

Cited by 3

Research of Parallel Processing Technology Based on Multi-Core

Xiang Li, Li Fei, Chang Hao Wang · Applied Mechanics and Materials · 2012

In this paper, five kinds of typical multi-core processers are compared from thread, cache, inter-core interconnect and etc. Two kinds of multi-core programming environments and some new programming languages are introduced. Thread-level speculation (TLS) and transactional memory (TM) are introduced to solve the problem of parallelization of sequential program. TLS automatically analyze and speculate the part of sequential process which can be parallel implement, and then automatically generate parallel code. TM systems provide an efficient and easy mechanism for parallel programming on multi-core processors. Typical TM likes TCC, UTM, LogTM, LogTM-SE and SigTM are introduced. Combined the TLS and TM can more effectively improve the sequential program running on the multi-core processors. Typical extended TM systems to support TLS likes TCC, TTM, PTT and STMlite are introduced.

Cited by 1

Designing and optimizing compute kernels on NVIDIA GPUs

Damir A. Jamsek · 2009

The availability of high performance compute capability in NVIDIA GPUs has expanded their use in CAD environments. We will describe the basic compute models including host/device programming models, device multi-thread programming models, as well optimization and performance tuning techniques.

Cited by 3

Performance Measurement of Processes and Threads Controlling, Tracking and Monitoring Based on Shared-Memory Parallel Processing Approach

Karzan Hussein Sharif, Subhi R. M. Zeebaree, Lailan M. Haji et al. · 2020

In this paper, a professional integrated operating system performance measurement system is proposed, designed, and implemented in order to monitor processes and threads. Because monitoring itself is not enough, so this system provides full control of the CPU forcing, Priority-changing, and pausing-resuming-killing of these processes/threads. During these complex operations, it provides the ability to measure/compute the details of Total-execution-time, CPU-time, User-time, Kernel-time, context switching, CPU -usage, and the priority of processes/threads. The proposed system can be used with any architecture of multicore processors. Despite that measuring all these parameters in one system is very difficult and complex especially the Kernel-time and Context-switching, but all of them have been applied and determined successfully. Adding to the above features that never been integrated (by any previous work) in one system, and in order to illustrate the real abilities of this system, a shared-memory parallel processing approach has been proposed and applied. The proposed system prepared to run all possible cases of processes and threads that construct under-tested-program which may be one of the: Single-Process-Single-Thread, Single-Process-Multi- Thread, Multi-Process-Single-Thread, Multi-Process-Multi- Thread, and Multi- Process-Single-Multi-Thread. The algorithms of this system are designed and implemented via C++ programming language(using C++ Standard Library Thread) which is the nearest programming to the OSs provides a more increasing processing speed.

Cited by 17

スレッドレベル並列処理プロセッサFUCEのハードウェア構成とその評価

松崎, 隆哲, Matsuzaki, Takanori, マツザキ, タカノリ et al. · Kyushu University Institutional Repository (QIR) (Kyushu University) · 2006

We are developing the FUCE processor based on the dataflow computing model. FUCE means FUsion of Communication and Execution. In order to execute many threads with multiple thread execution units efficiently, the FUCE processor executes multiple threads using the exclusive multi-thread execution model. The core concept of the exclusive multi-thread execution model is continuation based multi-thread execution, which is derived from dataflow computing. The FUCE processor unifies processing inside the processor and communication with processors outside as events, and executes the event as a thread. In this paper, we introduce the thread-programming model and the architecture of the FUCE processor and evaluate the hardware cost of a FUCE processor and the concurrency performance of a FUCE processor which we described in VHDL. As a result, we understood that the processor has concurrency capability when there is sufficient thread level parallelism.

Cited by 0Open access

Thread-Specific Storage for C/C++ An Object Behavioral Pattern for Accessing per-Thread State Efficiently

Douglas C. Schmidt, Nat Pryce, Timothy H. Harrison · 1998

In theory, multi-threading an application can improve performance (by executing multiple instruction streams simultaneously) and simplify program structure (by allowing each thread to execute synchronously rather than reactively or asynchronously). In practice, multi-threaded applications often perform no better, or even worse, than single-threaded applications due to the overhead of acquiring and releasing locks. In addition, multi-threaded applications are hard to program due to the complex concurrency control protocols required to avoid race conditions and deadlocks. This paper describes the Thread-Specific Storage pattern, which alleviates several problems with multi-threading performance and programming complexity. The Thread-Specific Storage pattern improves performance and simplifies multithreaded applications by allowing multiple threads to use one logically global access point to retrieve thread-specific data without incurring locking overhead for each access. 1 Intent Allows...

Cited by 20

Thread-Specific Storage for C/C++ -- An Object Behavioral Pattern for . . .

Douglas C. Schmidt, Nat Pryce, Timothy H. Harrison · 1997

In theory, multi-threading an application can improve performance (by executing multiple instruction streams simultaneously) and simplify program structure (by allowing each thread to execute synchronously rather than reactively or asynchronously). In practice, multi-threaded applications often perform no better, or even worse, than single-threaded applications due to the overhead of acquiring and releasing locks. In addition, multi-threaded applications are hard to program due to the complex concurrency control protocols required to avoid race conditions and deadlocks. This paper describes the Thread-Specific Storage pattern, which alleviates several problems with multi-threading performance and programming complexity. The Thread-Specific Storage pattern improves performance and simplifies multithreaded applications by allowing multiple threads to use one logically global access point to retrieve thread-specific data without incurring locking overhead for each access.

Cited by 0

Correct and Efficient Implementations of Synchronous Models on Asynchronous Execution Platforms ∗

2009

Concurrency is enjoying a second (or third? fourth?) youth. This is triggered by an anticipated revolution in the evolution of computer architecture, from faster, single-processor chips, to multi-processor chips with more and more processors [6]. This change brings hopes that the limits of Moore’s law will be overcome, but also fears that programming will become even harder than it already is. Indeed, parallel computing has been one of the holy grails of computer science. Concurrent programming today is predominantly thread-based. Thread-based concurrency is fundamentally asynchronous, in the sense that most thread-based models have an interleaving semantics, which stems from making few or no assumptions on the relative speeds of the threads. Thread communication is often based on some type of shared-memory model. This type of asynchronous concurrency results in nondeterministic behavior, which is hard to understand and debug. Indeed, a number of researchers claim that thread-based parallel programming is a bad idea [12, 9]. Other concurrency models, such as Kahn Process Networks [7], ensure deterministic results despite process interleaving. Unfortunately, most multi-processor architectures today do not follow such models, and use threads instead. Synchronous concurrency is based on a model that avoids interleaving. Instead, all processes execute in

Cited by 0