SAMI, MARIAGIOVANNA, SCIUTO, DONATELLA, SILVANO, CRISTINA et al. · Virtual Community of Pathological Anatomy (University of Castilla La Mancha) · 2005
An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.
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SpringerReference · 2011
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William S. Song, Jeremy Kepner, Vitaliy Gleyzer et al. · 2014
Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are hard-pressed to handle the throughput and memory requirements of graph computation. Lincoln Laboratory’s graph-processor architecture represents a fundamental rethinking of architectures. It utilizes innovations that include high-bandwidth three-dimensional (3D) communication links, a sparse matrix-based graph instruction set, accelerator-based architecture, a systolic sorter, randomized communications, a cacheless memory system, and 3D packaging. Many problems in computation and data
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T. Ikedo, William L. Martens · 2002
The paper describes trends in the development of multimedia processor architecture that may be predicted on the basis of the availability of an ASIC with 10s of millions of gates. Multimedia processing based upon multi granular parallelism for diverse media needs supercomputing power for multi threaded, process level execution. Due to the appearance of large scale integration (LSI) for what has been termed system on silicon, a new scheme for building the multimedia centric processor will be realized. The paper proposes advanced implementation technologies for multimedia acceleration employing a reconfigurable architecture and using hundreds of processing elements embedded within an ASIC. Accelerated functions considered in this proposal include 3D graphic and 3D audio rendering, and implementation of video and audio codecs. Computational efficiency for advanced applications, such as walk through virtual reality (VR), is maximized by sharing the results of geometric calculations that are required both for graphics and audio rendering.
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Marc de Kruijf, Karthikeyan Sankaralingam · 2011
Improving architectural energy efficiency is important to address diminishing energy efficiency gains from technology scaling. At the same time, limiting hardware complexity is also important. This paper presents a new processor architecture, the idempotent processor architecture, that advances both of these directions by presenting a new execution paradigm that allows speculative execution without the need for hardware checkpoints to recover from mis-speculation, instead using only re-execution to recover. Idempotent processors execute programs as a sequence of compiler-constructed idempotent (re-executable) regions. The nature of these regions allows precise state to be reproduced by re-execution, obviating the need for hardware recovery support. We build upon the insight that programs naturally decompose into a series of idempotent regions and that these regions can be large. The paradigm of executing idempotent regions, which we call idempotent processing, can be used to support various types of speculation, including branch prediction, dependence prediction, or execution in the presence of hardware faults or exceptions.
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Vítězslav Bátrla, Martin Děcký, Jakub Jermář · 2010
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Douglas J. Theis · Computer · 1981
Today's array processors provide a cost-effective tool for increasing the speed at which highly computation-bound processing jobs can be carried out. They are maturing and expanding with greatly improved hardware and software—improvements that are primarily a result of the accumulated experience of the vendors and users of these machines. All in all, it is a very competitive environment.
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SpringerReference · 2011
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Ján Mach, Lukáš Kohútka, Pavel Čičák · 2023
Processors for terrestrial applications are protected by Earth's atmosphere and magnetic field, so the probability of single event effects (SEE) is significantly lower. Shrinking of the technology nodes allows higher operational frequency and performance, but their susceptibility to SEE is increasing. Nowadays satellites and safety critical automotive applications require more and more computational power. The hardening by design has been implemented mainly by redundancy of the whole cores. The consequences are lower frequency, larger area, and higher power consumption. We propose a novel hardening technique, which enables high frequency operation and doesn't cause large power consumption and area overhead. The protection is based redundancy and separation of the pipeline into two main sections. It provides a fast detection of faults, simple recovery by flush of the pipeline, and allows a large prediction unit to be unprotected. The whole protection scheme can be implemented at the Register Transfer Level. We present the protection scheme at the core with RISC-V instruction set. Simulations confirm the protection can handle the injected faults. Synthesis shows, the protection lowers the maximum frequency by only about 4.7%. The area increase is only about 118% and can be even lower.
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Lundstrom, Stephen F., Shafer, Philip E., Barnes, George H. · NASA Technical Reports Server (NASA)
A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.
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D. R. McGregor, Nikolaos Kotsis · 2003
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Martin H. Weik · 2000
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2008
Abstract We present a novel decoupled branch processor architecture that separates controlflow information from computational instructions. The control-flow is encoded in an independent instruction stream, potentially providing benefits such as instruction cache prefetching, loop unrolling, code compression, reduced call/return overhead, and improved throughput. We discuss features and tradeoffs in the design and implementation of a branch processor architecture. We present a preliminary instruction set, and describe compilation strategies for the new architecture. We evaluate the architecture by studying metrics that impact its performance using the SPEC95 benchmark suite, and comment on the potential for using branch processor architectures to study control-flow issues in modern processors. 1.
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Nadia Nedjah, Luiza de Macedo Mourelle · 2023
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Victor Eijkhout · Society for Industrial and Applied Mathematics eBooks · 2026
Among the aspects of computer architecture relevant to high performance computing (HPC), probably the most important are the architectural details relating to memory and data movement inside the processor and between processor and memory. In this chapter we give a concise introduction to the memory subsystem of a computer; subsequent chapters will then apply this knowledge to coding for performance.
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寿倫 佐藤 · Medical Entomology and Zoology · 1999
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Damien Fétis, Romain Dolbeau, Antony Fraboulet et al. · 2004
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Simone Secchi, Antonino Tumeo, Oreste Villa · 2013
The SPARC (Scalable Processor ARChitecture) instruction set architecture is one of the most employed RISC design for multicore processors.The first 32-bit version of the architecture was introduced in 1986 with the name SPARC Version 7 (SPARCv7). In 1990, the next revision, SPARCv8, introduced integer multiply and divide instructions [1]. The current major revision, SPARCv9, moved the specification from a 32-to a 64-bit architecture [2]. Originally presented in 1993, the SPARCv9 architecture has since then been extended to support chip multithreading (CMT), hyperpriviliged processor instructions and mode of execution, SIMD extensions [3, 4, 5].
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Daniel Kusswurm · Apress eBooks · 2022
In the previous nine chapters, you learned about AVX, AVX2, and AVX-512. You also acquired the programming skills necessary to code C++ SIMD functions that exploited these x86 instruction set extensions to significantly accelerate the performance of a wide variety of algorithms. The chapter that you are about to read commences the second half of this book, which covers x86-AVX SIMD programming using x86-64 assembly language.
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Kenneth J. Thurber · CERN Document Server (European Organization for Nuclear Research) · 1979
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