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About 10,000 papers for “processor speed”

High-speed Josephson processor technology

S. Hasuo, S. Kotani, A. Inoue et al. · IEEE Transactions on Magnetics · 1991

High-speed operation of Josephson processors is demonstrated. They are a 4-b microprocessor, a 4-b processor, and an 8-b digital signal processor. Key technologies to realize these circuits are described from the viewpoint of circuit design. The technologies are a high-speed logic gate, named MVTL (modified variable threshold logic), and a three-phase sinusoidal power supply system. The MVTL gate has a large operating margin and high sensitivity. The MVTL gate family consists of OR, AND, 2/3 majority (MJ), and timed inverter (TI). Using these gates a variety of processors have been designed. These processors operate with three-phase power. The waveform is sinusoidal with DC-offset. This power supply system needs no latch and regulator circuit. This makes the processor very simple, and thus results in high-speed operation. To fabricate these processors, niobium junctions are very important, because they are reliable, uniform, controllable, and reproducible. High-speed gates, three-phase power supplies, and niobium junctions are indispensable for high-speed Josephson processors.

Cited by 26

High Speed Processor for FASTBUS

M. Campbell, S. Blatt, H. Kasha et al. · IEEE Transactions on Nuclear Science · 1981

This paper describes a processor designed to operate at a speed compatible with fastbus. It has been used in an experiment at the AGS in Brookhaven National Laboratory. Its function was to read data from various fastbus modules and store it in a buffer where it could later be read and further processed by a slower host computer. The data was formatted so that the host computer could more easily process it. The processor also made decisions based on the validity of the data and rejected bad events. The ratio of the number of triggers to the number of accepted events was about 20 to 1.

Cited by 2

High Speed Micro Signal Processor Study.

Gerald N. Shapiro · 1977

Abstract : This study defines a micro signal processor design based on maximum use of off-the-shelf IC functions, supplemented by special personalization of standard arrays. The signal processor elements can be grouped into Control, Memory and Arithmetic type elements. These elements are stackable into a variety of configurations because of the standardization applied to the data transfer timing. The processor design has a 24 bit multiword format with 2's complement arithmetic and processing capability of 25-40 million add/sec (where 1 multiply = 3 adds). (Author)

Cited by 3

Advanced Ultra High Speed Processor Technologies

Andrew A. Kostrzewski · 1996

Abstract : In Phase 1 of this project, POC designed, fabricated, and tested Optical interconnects, and designed a graphics processor based on field programmable gate arrays (FPGAs). P0C's board to board connection approach is based on multichannel integrated optical waveguides with novel optoelectronic active connectors, allowing multiple simultaneous data transfers among many boards. Data is transferred from chip to chip through optical data channels within an integrated chip. In the electronic processing System design, POC developed a preliminary design of a multiprocessor system suitable for single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) with video random access memory (VRAM) and static random access memory (SRAM) for main memory, look up table processing, and display interface.

Cited by 0

An ultra high-speed FFT processor

Kai Zhong, Hui He, Guangxi Zhu · 2003

This paper presents an implementation of an ultra high-speed FFT processor which can process input data of 800MHz sample rate. In order to meet such an extremely real-time requirement, high-speed differential I/O interfaces (LVDS) and dedicated parallel-pipelined radix-8 architecture are adopted. Implemented in an FPGA device, the processor can operate at 115MHz and compute a 4096-point complex FFT in 5μs. To reduce power consumption, currently, the chip is being migrated to 0.18 μm CMOS technology.

Cited by 8

A high-speed analog neural processor

P. Masa, Klaas Hoen, Hans Wallinga · IEEE Micro · 1994

Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight discretization, synapse nonlinearity, noise, and other non-ideal effects. Although our prototype does not take advantage of advanced CMOS technology, and was fabricated using a 2.5-μm CMOS process, it performs 6 billion multiplications per second, with only 2 W dissipation, and has as high as 1.5 Gbyte/s equivalent bandwidth.

Cited by 27Open access

High Speed Radix 8 CORDIC Processor

Jayashri Rudagi, Smt. S. Subbaraman · 2017

This paper presents high speed radix 8 CORDIC processor. Overall latency to estimate sine and cosine reduces 38% compared to that of radix 4 CORDIC processor. But hardware overhead increases due to additional adders and shifters required. The proposed design has been coded in Verilog and synthesized using Cadence RTL Encounter. PDP, EDP, and ADP parameters are estimated for radix 8 CORDIC processor and results are compared with respect to radix 4 CORDIC processor.

Cited by 0

Operational analysis of processor speed scaling

Kai Shen, Alex Zhang, Terence Kelly et al. · 2008

This brief announcement presents a pair of performance laws that bound the change in aggregate job queueing time that results when the processor speed changes in a parallel computing system. Our laws require only lightweight passive external observations of a black-box system and they apply to many commonly employed scheduling policies. By predicting the application-level performance impact of processing speed adjustments in parallel processors, including traditional SMPs and now increasingly ubiquitous multicore processors, our laws address problems ranging from capacity planning to dynamic resource allocation. Finally, our results show that operational analysis---an approach to performance analysis traditionally associated with commercial transaction processing systems---usefully complements existing parallel performance analysis techniques.

Cited by 8

High-speed multi-purpose VLSI digital processor

H. Tsou, A.S. Hamori, B.L. Troutman · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1983

A description is given of the architecture and design of a high-speed, multi-purpose VLSI digital processor for monolithic CMOS implementation. The architecture is optimized for high-speed arithmetic operations and for computer system applications either as a stand-alone processor or as an element in a network of processors. The internal three-stage pipeline organization enhances the throughput rate, with most of the instructions having an execution time of 200 ns. The chip design is based on 2-micron bulk CMOS with an estimated device count of 28300 devices, power of 400 milliwatts, and chip size of 250*365 mils. 10 references.

Cited by 1

Reconfigurable Processor Architecture For High Speed Applications

M. Aqeel Iqbal, Uzma Saeed Awan · 2009

Revolutions in the domain of computing have molded the structures and characteristics of computing systems. Conventional computing techniques involved the use of application specific integrated circuits to achieve a high performance at the cost of extremely inflexible hardware design meanwhile the flexibility of hardware design was achieved at the cost of slow speed processing by using programmable processors. The emergence of reconfigurable computing has filled the gap between the flexibility and performance of system. Reconfigurable computing combines the high speed of application specific integrated circuits with the flexibility of the programmable processors. The reconfigurable processors have further boosted up the dramatic nature of reconfigurable computing systems. These processors configure the most optimal and efficient hardware resources according to the demands of running application. The configured hardware resources can be modified or reconfigured later on according to the new demands of the running application. In this research paper reconfigurable processor architecture has been presented for high speed applications. The proposed reconfigurable processor is based on very long instruction word architecture. The proposed processor is using an efficient multi-threaded configuration controller and a multi-ported configuration memory to configure the multiple reconfigurable function units concurrently with minimum possible configuration overhead.

Cited by 1

High-Speed General Purpose Genetic Algorithm Processor

Pourya Hoseini, Sajjad Moshfe, Masoumeh Saber Zaeimian et al. · IEEE Transactions on Cybernetics · 2015

In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

Cited by 30

Portable high-speed biomass processor for Chunkwood

W.A. Aikins · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1992

All the design tasks for the Chunker/baler machine have been completed. The multiple blade shearing system and the chunkwood baler were very challenging. I believe if there was a market for chunkwood, the redesigned Chunker would be a viable marketable product. It appears however that at best the market is very limited and would not justify an investment either by me or a possible licensee at this time. I do believe however, that eventually the costs for fossil fuels are going to rise to the point that chunkwood will be a profitable product. When this time arrives, we will have a god machine waiting in the wings to fill this future need.

Cited by 0Open access

High-Speed Beam Signal Processor for SHINE

Longwei Lai, Yongbin Leng · JACOW · 2019

A CW hard X-ray FEL is under construction in SSRF, which pulse rate is designed to 1MHz. A new high-speed sampling BPM signal processor is under development to meet the high performance requirements of beam position measurement system. The processor¿s sampling rate can be up to 500MHz, and beam position information of each bunch (1MHz rate) can be retrieved with the power of FPGA. Time stamp is aligned with the position data for offline analysis. The processor is designed to be a common signal processing platform for beam diagnostics. The first application is cavity BPM, and other applications, including button BPM, stripline BPM, and even wire scanner processor will be developed based on this platform. At the same time, a RF direct sampling processor is designed for cavity BPM signal processing. This novel technology will greatly simplify the cavity BPM electronic system, and make the system design more efficient and more flexible.

Cited by 1Open access

High speed FFT processor consuming optimal power

P. V. Karthik, G. Bhrigu Rishi, G Chandu Sagar · 2016

Implementation of a FFT processor using pipelining and folding techniques which is achieved by reducing number of functional units, registers and multiplexers. The pipelining and parallel processing techniques deals with the reducing the critical path which in turns increases the speed of the processor, in order achieve high speed, special kind of multipliers and adders are used. The folding transformation is used to systematically determine the control circuits in DSP architectures where multiple algorithm operations (such as addition operations) are time multiplexed to a single functional unit. By executing multiple algorithm operations on a single function unit, the number of functional units in the implementation is reduced resulting in an integrated circuit with low silicon area.

Cited by 0

Design of a High Speed FFT Processor

Belma Joseph, S Jayanthy, Sri Ramakrishna · 2014

Abstract-- The Discrete Fourier Transform (DFT) is used to transform the samples in time domain into frequency domain coefficients. The Fast Fourier Transform (FFT) is a widely used algorithm that computes the Discrete Fourier Transform (DFT) using much less operations than a direct realization of the DFT. FFTs is of great significance to a wide variety of applications such as data compression, spectral analysis etc. This paper proposes a design that implements a Fast Fourier transform (FFT). The module is developing by Radix-2, Radix-4 decimation in time algorithm structure. The operation of the FFT processor performs three main processes i.e. data load, compute and result unload. The processing cycle starts with the data load process. In this process sampled data is read in and stored in memory. During the compute process computation of FFT on the stored data is performed and result unloaded process makes the FFT results available at its output. This paper also compares the performance of Radix-2 algorithm with Radix-4 algorithm. Keywords-- DFT, FFT, Processor, Radix-2 algorithm, Radix-4 algorithm

Cited by 0