Nan Ye, Ziyu Hao, Xianghui Xie · 2013
Integrating a large number of simple cores on the chip to provide the desired performance and throughput, microprocessor has entered the many core era. In order to fully extract the ability of the many core processor, we propose speedup models for many core architecture in this paper. Under the assumption of Hill-Marty model, we deduce our formulas based on Gustafson's Law and Sun-Ni's Law. Then, compared with the Hill-Marty model, we theoretically analyze the best allocation under the given resources. Furthermore, we apply the conclusions of our models to evaluate current many core processors and predict concrete future architecture. Our results show that the many core architecture is capable of extensive scalability and being beneficial to promote the performance, especially heterogeneous one. By using simple analytical models, we provide a better understanding of architecture design and our work complement existing studies.
Cited by 5
Farhad Ebrahimi-Azandaryani, Dietmar Fey · Lecture notes in computer science · 2025
Cited by 0
Yue Luo, Lizy K. John · IEEE Computer Architecture Letters · 2004
Cycle accurate simulation of processors is extremely time consuming. Sampling can greatly reduce simulation time while retaining good accuracy. Previous research on sampled simulation has been focusing on the accuracy of CPI. However, most simulations are used to evaluate the benefit of some microarchitectural enhancement, in which the speedup is a more important metric than CPI. We employ the ratio estimator from statistical sampling theory to design efficient sampling to measure speedup and to quantify its error. We show that to achieve a given relative error limit for speedup, it is not necessary to estimate CPI to the same accuracy. In our experiment, estimating speedup requires about 9X fewer instructions to be simulated in detail in comparison to estimating CPI for the same relative error limit. Therefore using the ratio estimator to evaluate speedup is much more cost-effective and offers great potential for reducing simulation time. We also discuss the reason for this interesting and important result.
Cited by 21
Nguyen Thi Anh Thu, Raj Vaswani, John Zahorjan · 1996
We address the problem of maximizing application speedup through runtime, self-selection of an appropriate number of processors on which to run. Automatic, runtime selection of processor allocations is important because many parallel applications exhibit peak speedups at allocations that are data or time dependent. We propose the use of a runtime system that: (a) dynamically measures job efficiencies at different allocations, (b) uses these measurements to calculate speedups, and (c) automatically adjusts a job's processor allocation to maximize its speedup. Using a set of 10 applications that includes both hand-coded parallel programs and compiler-parallelized sequential programs, we show that our runtime system can reliably determine dynamic allocations that match the best possible static allocation, and that it has the potential to find dynamic allocations that outperform any static allocation. 1. Introduction We consider the problem of maximizing the speedup of an individual paral...
Cited by 3
Kuo‐Chan Huang, Tse-Chi Huang, Yuan-Hsin Tung et al. · Smart innovation, systems and technologies · 2012
Cited by 6
Mehmet Çelenk · Parallel algorithms and applications · 1993
Several low-level vision algorithms have been implemented on a 16-node hypercube processor (AMETEK S-14) by exploitation of its network embedding feature. This includes edge detection with the Sobel operator, histogramming, one-pass parallel binary image thinning, and noise-cleaning. The primary objective is to parallelize these algorithms by achieving a proper image-to-processor topology mapping and to determine the actual speedup factor of parallel implementation over the sequential programming. Two basic topologies used are the ring and the nearest-neighbor networks, which are mapped onto the hypercube system. Several 512 × 512 gray-level images have been processed concurrently. A tenfold improvement in the speedup has been obtained compared to the sequential implementation in a single processor of the concurrent system. This result is obtained by ignoring the host-to-node, node-to-host, and I/O communications.
Cited by 1
D.L. Lee, Mokhtar Aboelaze · 2005
Cited by 1
Kridsadakorn Chaichoompu, Surin Kittitornkun, Sissades Tongsima · Bioinformation · 2007
Many computational intensive bioinformatics software, such as multiple sequence alignment, population structure analysis, etc., written in C/C++ are not multicore-aware. A multicore processor is an emerging CPU technology that combines two or more independent processors into a single package. The Single Instruction Multiple Data-stream (SIMD) paradigm is heavily utilized in this class of processors. Nevertheless, most popular compilers including Microsoft Visual C/C++ 6.0, x86 gnu C-compiler gcc do not automatically create SIMD code which can fully utilize the advancement of these processors. To harness the power of the new multicore architecture certain compiler techniques must be considered. This paper presents a generic compiling strategy to assist the compiler in improving the performance of bioinformatics applications written in C/C++. The proposed framework contains 2 main steps: multithreading and vectorizing strategies. After following the strategies, the application can achieve higher speedup by taking the advantage of multicore architecture technology. Due to the extremely fast interconnection networking among multiple cores, it is suggested that the proposed optimization could be more appropriate than making use of parallelization on a small cluster computer which has larger network latency and lower bandwidth.
Cited by 2Open access
Xufeng Chen, Deshi Ye · Discrete Optimization · 2016
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D.-L. Lee, Wayne A. Davis · 2002
Linear speedup of two-dimensional neighborhood functions requires that the underlying processor perform iterative operations and solve the window border problem simultaneously. The authors illustrate a solution to the window border problem using an array processor that provides conflict-free access and alignment of two types of square block vectors of two-dimensional arrays. They give a parallel algorithm embodying this solution, which can speedup a class of neighborhood functions by a factor directly proportional to the number of processing elements in the array processor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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W. Eppler, Oscar Firschein, G. McCulley et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1979
Algorithms for the automatic detection of defects, such as cracks and cavities in radiographs of artillery shells have been previously described. An array processor mechanization of these algorithms is now described that allows a 200 x 300 pixel array to be analyzed in less than 10 seconds. The algorithms were restructured to take advantage of the vector orientation of the array processor.
Cited by 2
Mehdi Kamal, Ali Afzali‐Kusha, Saeed Safari et al. · ACM Journal on Emerging Technologies in Computing Systems · 2014
In this article, we investigate the impact of process variations on the speedup and maximum frequency of the extended ISA processor. First, without considering process variations, a custom functional unit (CFU) is designed based on nominal timing parameters, then the timing variations of critical paths of the extensible processor, including the baseline processor and the CFU, are investigated by considering both systematic and random variations. Next, the maximum frequency of the extensible processor and the speed enhancement factor of the extended ISA for different benchmarks are investigated. Results show that timing variation could reduce the speedup of the extensible processor. However, this reduction is highly dependent on the baseline processor and the CFU structures. Additionally, the impact of process variations in the worst-case design approach is studied. Results show that the speedup of the extensible processor is reduced more than in the case when custom instructions (CIs) are selected without considering process variations. To study the impact of each variation type, speedup variations due to random and systematic variations are investigated separately. The study reveals that random variation has a similar effect on the CFU and the baseline processor, while the impact of systematic variation on the baseline processor is greater than the CFU.
Cited by 2
Nathan Tuck, et al. · 2003
This paper analyzes an Intel Pentium 4 hyper-threading processor. The focus is to understand its performance and the underlying reasons behind that performance. Particular attention is paid to putting the processor in context with prior published research in simultaneous multithreading -- validating and re-evaluating, where appropriate, how this processor performs relative to expectations. Results include multiprogrammed speedup, parallel speedup, as well as synchronization and communication throughput. The
Cited by 0
The Intel, Ö Pentium, Ö Hyper-threading · 2008
This paper analyzes an Intel Pentium 4 hyper-threading processor. The focus is to understand its performance and the underlying reasons behind that performance. Particular attention is paid to putting the processor in context with prior published research in simultaneous multithreading – validating and re-evaluating, where appropriate, how this processor performs relative to expectations. Results include multiprogrammed speedup, parallel speedup, as well as synchronization and communication throughput. The processor is also evaluated in the context of prior work on the interaction of multithreading with the operating system and compilation.
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Todd Austin · RIT Scholar Works (Rochester Institute of Technology) · 1990
One way to increase the performance of a processing unit is to exploit implicit parallelism. Exploiting this parallelism requires a processor to dynamically select instructions in a serial instruction stream which can be executed in parallel. As operations are computed concurrently, an execution speedup will occur. This thesis studies how effectively implicit parallelism could be exploited in the Scalable Pro cessor Architecture (SPARC)[9], a reduced instruction set architecture developed by Sun Microsystems. First an analysis of SPARC instruction traces will determine the optimal speedup that would be realized by a processor with infinite resources. Next, an analytical model of a parallelizing processor will be developed and used to predict the effects of limited resources on optimal speedup. Lastly, a SPARC simulator will be employed to determine the actual speedup of resource limited configurations, and the results will be correlated with the analytical model.
Cited by 0Open access
Robert I. Davis, Thomas Rothvoß, Sanjoy K. Baruah et al. · 2012
Keywords: Real-time Uniprocessor Fixed priority pre-emptive scheduling Earliest Deadline First (EDF) Suboptimality Processor speedup factor Constrained deadline Implicit deadline Omega constant This paper examines the relative effectiveness of fixed priority pre-emptive scheduling in a uniprocessor system, compared to an optimal algorithm such as Earliest Deadline First (EDF). The quantitative metric used in this comparison is the processor speedup factor, equivalent to the factor by which processor speed needs to increase to ensure that any taskset that is schedulable according to an optimal scheduling algorithm can be scheduled using fixed priority pre-emptive scheduling, assuming an optimal priority assignment policy. For constrained-deadline tasksets where all task deadlines are less than or equal to their periods, the maximum value for the processor speedup factor is shown to be 1/ Ω ≈ 1. 76322, (where Ω is the mathematical constant defined by the transcendental equation ln ( 1/ Ω) = Ω, hence, Ω ≈ 0.567143). Further, for implicit-deadline tasksets where all task deadlines are equal to their periods, the maximum value for the processor speedup factor is shown to be 1/ln(2) ≈ 1.44270. The derivation of this latter result provides an alternative proof of the well-known Liu and Layland result. 1.
Cited by 0
Kridsadakorn Chaichoompu, Surin Kittitornkun · 2008
Speedup bioinformatics applications on multicorebased processor using vectorizing and multithreading strategies
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Martin Schoeberl · 2007
In this paper we investigate the overheads of object-oriented operations, such as virtual method dispatch and field access, in the context of an embedded processor for real-time systems. As an example we use a Java processor that implements those operations in microcode similar to the way those operations are compiled to a RISC processor. As this processor is a soft-core, implemented in an FPGA, an optimization of those operations is a valuable option. Significant application speedup is possible by providing an architecture for object-oriented programming languages. We also evaluate the hardware cost of this optimization with respect to the application speedup.
Cited by 15
John R. Gurd, Chris Kirkham, Ian Watson · Communications of the ACM · 1985
The Manchester project has developed a powerful dataflow processor based on dynamic tagging. This processor is large enough to tackle realistic applications and exhibits impressive speedup for programs with sufficient parallelism.
Cited by 465Open access
Ghodrat, Mohammad Ali, Givargis, Tony, Nicolau, Alex · eScholarship (California Digital Library) · 2009
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for significant performance increase. The transformation technique optimizes loops containing nested conditional blocks. Specifically, the transformation takes advantage of the fact that the Boolean value of the conditional expression, determining the true/false paths, can be statically analyzed using a novel interval analysis technique that can evaluate conditional expressions in the general polynomial form. Results from interval analysis combined with loop dependency information is used to partition the iteration space of the nested loop. In such cases, the loop nest is decomposed such as to eliminate the conditional test, thus substantially reducing the execution time. Our technique completely eliminates the conditional from the loops (unlike previous techniques) thus further facilitating the application of other optimizations and improving the overall speedup. Applying the proposed transformation technique on loop kernels taken from Mediabench, SPEC-2000, mpeg4, qsdpcm and gimp, on average we measured a 2.34X speedup when running on a UltraSPARC processor, a 2.92X speedup when running on an Intel Core Duo processor, a 2.44X speedup when running on a PowerPC G5 processor and a 2.04X speedup when running on an ARM9 processor. Performance improvement, taking the entire application into account, was also promising: for 3 selected applications (mpeg-enc, mpeg-dec and qsdpcm) we measured 15% speedup on best case (5% on average) for the whole application.
Cited by 0Open access