Suresh Babu, Balaji · Zenodo (CERN European Organization for Nuclear Research) · 2025
This paper presents a new non-iterative algorithm for computing square roots efficiently. The computation of square roots has been a fundamental mathematical operation for thousands of years, with numerous algorithms developed throughout history. From the Babylonian method to Newton-Raphson iteration and modern hardware implementations, mathematicians and computer scientists have continually sought faster and more accurate approaches. Despite this rich history, most square root algorithms share a common limitation: they require iterative processes to achieve high precision. This paper introduces a new non-iterative formula that calculates square roots with remarkable accuracy in a single computational step, offering potential advantages for applications where computational efficiency is paramount. Contact: https://www.linkedin.com/in/balaji-suresh-739a231a9/
Cited by 0Open access
Christopher J. Musial · Elsevier eBooks · 1991
Cited by 1
Oklobdzija, Ercegovac · IEEE Transactions on Computers · 1982
In this correspondence a systematic derivation of an on-line square root algorithm is presented. The algorithm operates on variables represented in the normalized radix r floating-point system in a digit-by-digit fashion with an on-line delay of 1. The approach used in deriving the square root algorithm is described in detail. The basic characteristics of hardware-level implementation are also discussed.
Cited by 43
Keith Hirst · Journal of the London Mathematical Society · 1972
Cited by 0
Amir Kaivani, Seok‐Bum Ko · Circuits Systems and Signal Processing · 2013
Cited by 4
Christoph Kreitz · 2008
In a constructive setting, the formula ∀n ∃r r2≤n ∧ n<(r+1)2 specifies an algorithm for computing the integer square root r of a natural number x. A proof for this formula implicitly contains an integer square root algorithm that mirrors the way in which the formula was proven correct. In this note we describe the formal derivation of several integer square root algorithms within the Nuprl proof development system and show how efficient algorithms can be derived using advanced induction schemes. 1 Deriving a Linear Algorithm The standard approach to proving ∀n ∃r r2≤n ∧ n<(r+1)2 is induction on n, which will lead to the following two proof goals Base Case: prove ∃r r2≤0 ∧ 0<(r+1)2 Induction Step: prove ∃r r2≤n+1 ∧ n+1<(r+1)2 assuming ∃rn r2≤n ∧ n<(rn+1)2. The base case can be solved by choosing r = 0 and using standard arithmetical reasoning to prove the resulting proof obligation 02≤0 ∧ 0<(0+1)2. In the induction step, one has to analyze the root rn. If (rn+1)2≤n+1, then choosing r = rn+1
Cited by 0
Boccacci, Patrizia, De Mol, Christine, Loris, Ignace · Dépôt institutionnel de l'Université libre de Bruxelles (Université Libre de Bruxelles) · 2024
info:eu-repo/semantics/published
Cited by 0
Patrizia Boccacci, Christine De Mol, Ignace Loris · Inverse Problems · 2025
Abstract In the framework of sparsity-enforcing regularisation for linear inverse problems, we consider the minimisation of a square-root Lasso cost function. To solve this problem we devise a simple modification of the iterative soft-thresholding algorithm (ISTA) for the Lasso problem and we prove convergence for this algorithm, which we call SQRT-ISTA. Under some additional assumptions, we derive an upper bound on the convergence rate of the cost function. We also generalise these results to the case of the group square-root Lasso, where sparsity is enforced for groups of variables instead of individual ones.
Cited by 0
Mariusz Węgrzyn, Stepan Voytusik, Наталія Гавкалова · Journal of Telecommunications and Information Technology · 2025
The coordinate rotation digital computer (CORDIC) algorithm is a popular method used in many fields of science and technology. Unfortunately, it is a time-consuming process for central processing units (CPUs) and graphics processing units (GPUs), and even for specialized digital signal processing (DSP) solutions. The CORDIC algorithm is an alternative for Newton-Raphson numerical calculation and for the FPGA based resource-expensive look-up-table (LUT) method. Various modifications of the CORDIC algorithm allow to speed up the operation of hardware in edge computing devices. With that context taken into consideration, this article presents a fast and accurate square root floating point (SQRT FP) CORDIC function which can be implemented in field programmable gate arrays (FPGAs). The proposed algorithm offers low-complexity, decent accuracy and speed, and is sufficient for digital signal processing (DSP) applications, such as digital filters, accelerators for neural networks, machine learning and computer vision applications, and intelligent robotic systems.
Cited by 1Open access
Yun Wang, Jinkuan Wang · 2007
A fast square-root detection algorithm for V-BLAST is proposed to improve the high complexities when conventional square-root detection algorithm detects in MIMO receivers. It simplifies the computing process of conventional square-root detection algorithm and proposes a parallel processing algorithm of decided signal's feedback and received signal's interference cancellation. The detection complexities of the algorithm are reduced 38.24% and 16% compared to the conventional and improved square-root detection algorithm, while the detection performances retain. Under the environment of multiple scattering wireless communication, the simulation experiment results show that compared to the conventional square-root detection algorithm, the detection complexities of the proposed algorithm reduces while the detection performances retain.
Cited by 4
Armand Stefan Rotaru, Sorin Iftene · Fundamenta Informaticae · 2013
Atkin's algorithm [2] for computing square roots in $Z^*_p$ , where p is a prime such that p ≡ 5 mod 8, has been extended by Müller [15] for the case p ≡ 9 mod 16. In this paper we extend Atkin's algorithm to the general case p ≡ 2 s + 1 mod 2 s + 1, for any s ≥ 2, thus providing a complete solution for the case p ≡ 1 mod 4. Complexity analysis and comparisons with other methods are also provided.
Cited by 5
Puneet Kachhwal, Bikash Chandra Rout · 2014
Square root is a basic arithmetic operation which is used in digital signal processing. Due to complex algorithm it is difficult to implement on FPGA. This paper presents a novel square root algorithm which is based on some ancient Indian mathematics (Vedic mathematics) formula called Dwandwa Yoga. The proposed algorithm uses lowest area. In this paper we are using 24-bit (16bit+8bit) floating point input and 16-bit (8bit+8bit) floating point output. We will discuss the proposed square root algorithm, its hardware description, and its FPGA implementation using Xilinx tool. The cost for this algorithm on the SPARTAN-3E XC3S500E is 173 LUTs (4 input), 90 slices, 99 slice flip flops. The design consumes 90.9 mW power and can be operated at frequency 68.22MHz. This algorithm uses only adders, subtractors and registers which leads to consume less area, less power and high operating frequencies. The proposed algorithm can be implemented on decimal numbers.
Cited by 15
Patrizia Boccacci, Christine De Mol, Ignace Loris · ArXiv.org · 2025
In the framework of sparsity-enforcing regularisation for linear inverse problems, we consider the minimisation of a square-root Lasso cost function. To solve this problem we devise a simple modification (called SQRT-ISTA) of the Iterative Soft-Thresholding Algorithm (ISTA) for the Lasso problem and we prove convergence for this algorithm. Under some additional assumptions, we derive an upper bound on the convergence rate of the cost function. We also generalise these results to the case of the group square-root Lasso, where sparsity is enforced for groups of variables instead of individual ones.
Cited by 0Open access
J. Bannur, A. Varma · 1985
VLSI implementation of a square root algorithm is studied. Two possible implementations of the basic non-restoring algorithm are presented — the second is more area-efficient and modular than the first. The implementations are simple and easy to control, but, at the same time, are more area-time efficient than many existing designs. A hardware algorithm suited to microprogram implementation is also given. Extension of the algorithms to achieve ½ bit precision is discussed.
Cited by 16
Lu, Mi · Figshare · 2021
A parallel square-root algorithm together with its systolic arrays implementation are proposed for performing the modified extended Kalman filter (MEKF). The proposed parallel square-root algorithm is designed based on the singular value decomposition (SVD) and the Faddeev algorithm, and a very large scale intergration (VLSI) systolic arrays architecture is developed for its implementation. Comparing with other square root Kalman filtering algorithms existing in literature, the proposed method is more numerically stable. Moreover, the new VLSI architecture has very nice parallel and pipelining characteristics in applying the MEKF and achieves higher efficiency. For n-dimensional state vector estimations, the proposed architecture consists of O(2n<sup>2</sup>) processing elements and uses O((s + 17)n) time-steps for a complete iteration at each instant, in contrast to the complexity of O((s + 6)n<sup>3</sup>) time-steps for a sequential implementation, where s ≈ log n.
Cited by 0Open access
Hanebeck, Uwe D. · Repository KITopen (Karlsruhe Institute of Technology) · 2001
This paper presents a modified set theoretic framework for estimating the state of a linear dynamic system based on uncertain measurements. The measurement errors are assumed to be unknown but bounded by ellipsoidal sets. Based on this assumption, a recursive state estimator is (re–)derived in a tutorial fashion. It comprises both the prediction step (time update), i.e., propagation of a set of feasible states by means of the system model and the filter step (measurement update), i.e., inclusion of a new measurement into the current estimate. The main contribution is an efficient square–root formulation of this estimator, which is well suited especially for practical applications.
Cited by 0Open access
Feng Wang, Yasuyuki Nogami, Yoshitaka Morikawa · 2008
Abstract. A square root (SQRT) algorithm in GF (p m)(m=r0r1 ···rn−12 d, ri: odd prime, d&gt;0: integer) is proposed in this paper. First, the Tonelli-Shanks algorithm is modified to compute the inverse SQRT in GF (p 2d where most of the computations are performed in the corresponding sub-fields GF (p 2i) for 0 i d − 1. Then the Frobenius mappings with an addition chain are adopted for the proposed SQRT algorithm, in which a lot of computations in a given extension field GF (p m) are also reduce to those in a proper subfield by the norm computations. Those reductions of the field degree increase efficiency in the SQRT implementation. More specifically the Tonelli-Shanks algorithm and the proposed algorithm in GF (p 22), GF (p 44) and GF (p 88) were implemented on a Pentium4 (2.6 GHz) computer using the C++ programming language. The computer simulations showed that, on average, the proposed algorithm accelerates the SQRT computation by 25 times in GF (p 22), by 45 times in GF (p 44), and by 70 times in GF (p 88), compared to the Tonelli-Shanks algorithm, which is supported by the evaluation of the number of computations. 1
Cited by 0
Lei Wang, Crec Railway · 2011
A new iterative square root algorithm is proposed to improve the precision of square root which is the sum of two squares.Taylor series is introduced to derive the formula by using the first polynomial as the initial value.The optimal coefficient of the first polynomial with minimal error is obtained based on the analysis of maximal error when the coefficient is distributed in different scope.Further,the practical coefficient of the first polynomial and iterative algorithm of square root is proposed,which is essentially same as Newton iteration method,but does not need to consider the initial value selection,and the precision depends on iteration times.The simulation shows that the computation complexity of the proposed algorithm is similar to the traditional method,but the precision is increased by 100 times.The maximal error is below the 0.002% and it meets the requirement of microprocessor protection.
Cited by 1
Edward C. Tarte · Mathematics Teacher Learning and Teaching PK-12 · 1974
The procedure discussed in this article leads the student to discover step by step the square root algorithm.
Cited by 0
Matti Tommiska · 2002
An area-efficient implementation of a fast-converging square-root algorithm is presented. The design of special arithmetic operations differs in many ways from the traditional tasks that digital designers are used to, and the role of parameterizability and mapping of mathematical algorithms onto digital hardware is discussed. Certain real-world applications requiring the use of the square-root operator are presented, and it is argued that implementing special arithmetic operations directly in hardware offers significant speed advantages over the conventional approach of implementing them in software. The mathematical algorithm of the square-root operator is described, and its applicability to an implementation in digital logic is presented. It also is shown that the square-root operator can be efficiently implemented without the need to resort to multiplications or divisions, which is advantageous in terms of both area and timing.
Cited by 18