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About 1,175 papers for “thread-level parallelism”

Thread Level Parallelism of Desktop Applications

Krisztián Flautner, Rich Uhlig · 2000

Multiprocessing is already prevalent in servers, where multiple clients present an obvious source of thread level parallelism. The case for multiprocessing is less clear for desktop applications, however processor architects are already designing processors that count on the availability of concurrently runnable threads. In this paper we examine a wide variety of existing desktop workloads (over 50) across three different operating systems (Windows NT, BeOS and Linux) and quantify the amount and nature of thread level parallelism (TLP) in the system. Our results show that OS and application structure have a significant effect on TLP. While most of the workloads exhibit only moderate amounts of parallelism (under 1.5), there is evidence that show that many of these workloads are not inherently single threaded. 1. Introduction Processor architects are increasingly looking at support for multithreaded workloads. A new generation of processors such as the IBM Power4 [3], Compaq EV8 [4] a...

Cited by 0

Exploiting thread-level parallelism on reconfigurable architectures

Amir Momeni · 2017

Field Programmable Gate Arrays (FPGAs) are one major class of architectures commonly used in parallel computing systems. FPGAs provide a massive number (i.e., millions) programmable logic blocks and I/O cells, as well as programmable interconnects, which can be configured for a particular application. This reconfigurable architecture is flexible and power efficient, and potentially, provides better floating-point operations per watt rates versus general purpose architectures, such as CPUs and GPUs. However, programming an FPGA can be challenging and time-consuming, requiring hardware description language (HDL) experience and digital design expertise. High-level synthesis (HLS) tools have been designed to ease the FPGA programming task by generating HDL (e.g., Verilog or VHDL) codes from high-level languages (e.g., C/C++, OpenCL). Inparticular, there have been recent developments in OpenCL-based HLS tools (OpenCL-HLS) to enable programmers to construct a customized data-path that can best match a parallel application, relieving the programmer of many implementation details.

Cited by 0Open access

Software thread integration for instruction-level parallelism

Won So, Alexander G. Dean · ACM Transactions on Embedded Computing Systems · 2013

Multimedia applications require a significantly higher level of performance than previous workloads of embedded systems. They have driven digital signal processor (DSP) makers to adopt high-performance architectures like VLIW (Very-Long Instruction Word). Despite many efforts to exploit instruction-level parallelism (ILP) in the application, the speed is a fraction of what it could be, limited by the difficulty of finding enough independent instructions to keep all of the processor's functional units busy.

Cited by 2

In Search of Speculative Thread-Level Parallelism

Jeffrey Oplinger, D. Heine, Monica S. Lam · 1999

parallelization scheme or machine model (or both) that should be improved.As a consequence, poor results may not reflect any inherent limitations of the STP model, but rather the way it was applied.

Cited by 30

Abstract Thread level parallelism of desktop applications

2008

Multiprocessing is already prevalent in servers, where multiple clients present an obvious source of thread level parallelism. The case for multiprocessing is less clear for desktop applications, however processor architects are already designing processors that count on the availability of concurrently runnable threads. In this paper we examine a wide variety of existing desktop workloads (over 50) across three different operating systems (Windows NT, BeOS and Linux) and quantify the amount and nature of thread level parallelism (TLP) in the system. Our results show that OS and application structure have a significant effect on TLP. While most of the workloads exhibit only moderate amounts of parallelism (under 1.5), there is evidence that show that many

Cited by 0

SpMT WaveCache: Exploiting Thread-Level Parallelism in WaveScalar

Songwen Pei, Baifeng Wu, Min Du et al. · 2009

Speculative multithreading (SpMT) increases the performance by means of executing multiple threads speculatively to exploit thread-level parallelism. By combining software and hardware approaches, we have improved the capabilities of previous WaveScalar ISA on the basis of transactional memory system for the WaveCache Architecture. Threads are extracted at the course of static compiling, and speculatively executed as a thread-level transaction that is supported by extra hardware components, such as thread-context-table (TCT) and thread-memory-history (TMH). We have evaluated the SpMT WaveCache with 6 real benchmarks from SPEC, Mediabench and Mibench. On the whole, the SpMT WaveCache outperforms superscalar architecture ranging from 2times to 3times, and great performance gains are achieved over original WaveCache and transactional WaveCache as well.

Cited by 3

Realization of Thread Level Parallelism on Quantum Devices

Li, Keren, Lin, Zidong, An, Zheng et al. · ArXiv.org · 2025

Scaling up quantum devices is a central challenge for realizing practical quantum computation. Modular quantum architectures promise scalability, yet experiments to date have relied on either $\sim\!10^{3}$-qubit monolithic chips or fragile interconnects with high loss. Here, we introduce a classical linkage scheme that merges multiple independent quantum processing units (QPUs) into a single logical device, enabling thread-level parallelism (TLP). Theoretically, we show that quantum routines with product-state inputs and low-rank entangling layers can be re-expressed in an efficient parallelizable form. Experimentally, we validate this architecture on clusters comprising up to sixteen benchtop nuclear magnetic resonance (NMR) quantum nodes. A four-qubit Greenberger-Horne-Zeilinger (GHZ) state is partitioned into parallel two-qubit subcircuits, achieving a fidelity of $93.8\,\%$ with respect to the ideal state. A non-Hermitian evolution, implemented via a truncated Cauchy integral on Hermitian Hamiltonians, reproduces exact observables with high accuracy. Our results demonstrate that classical links suffice to scale up the logical size of quantum computations and realize general, non-unitary channels on today's hardware, opening an experimentally accessible route toward software-defined, clustered quantum accelerators.

Cited by 0Open access

Exploiting Thread-Level Parallelism to Build Decision Trees

Karsten Steinhaeuser, Nitesh V. Chawla, Peter M. Kogge · 2008

Abstract. Classification is an important data mining task, and decision trees have emerged as a popular classifier due to their simplicity and relatively low computational complexity. However, as datasets get extremely large, the time required to build a decision tree still becomes intractable. Hence, there is an increasing need for more efficient tree-building algorithms. One approach to this problem involves using a parallel mode of computation. Prior work has successfully used processor-level parallelism to partition the data and computation. We propose to use Cray’s Multi-Threaded Architecture (MTA) and extend the idea by employing thread-level parallelism to reduce the execution time of the tree building process. Decision tree building is well-suited for such low-level parallelism as it requires a large number of independent computations. In this paper, we present the analysis and parallel implementation of the ID3 algorithm, along with experimental results. 1

Cited by 0

Realization of Thread Level Parallelism on Quantum Devices

Li, Keren, Lin, Zidong, An, Zheng et al. · arXiv (Cornell University) · 2025

Scaling up quantum devices is a central challenge for realizing practical quantum computation. Modular quantum architectures promise scalability, yet experiments to date have relied on either $\sim\!10^{3}$-qubit monolithic chips or fragile interconnects with high loss. Here, we introduce a classical linkage scheme that merges multiple independent quantum processing units (QPUs) into a single logical device, enabling thread-level parallelism (TLP). Theoretically, we show that quantum routines with product-state inputs and low-rank entangling layers can be re-expressed in an efficient parallelizable form. Experimentally, we validate this architecture on clusters comprising up to sixteen benchtop nuclear magnetic resonance (NMR) quantum nodes. A four-qubit Greenberger-Horne-Zeilinger (GHZ) state is partitioned into parallel two-qubit subcircuits, achieving a fidelity of $93.8\,\%$ with respect to the ideal state. A non-Hermitian evolution, implemented via a truncated Cauchy integral on Hermitian Hamiltonians, reproduces exact observables with high accuracy. Our results demonstrate that classical links suffice to scale up the logical size of quantum computations and realize general, non-unitary channels on today's hardware, opening an experimentally accessible route toward software-defined, clustered quantum accelerators.

Cited by 0Open access

Exploiting thread-level parallelism on simultaneous multithreaded processors

Jack Lo, Susan J. Eggers, Henry M. Levy · 1998

This dissertation investigates techniques for promoting constructive sharing and efficient utilization of processor resources on simultaneous multithreaded processors. Simultaneous multithreading is an architecture that permits multiple threads to issue multiple instructions to the functional units each cycle. By dynamically sharing processor resources both temporally and physically, simultaneous multithreading can avoid the resource partitioning and inflexibility that plague other parallel architectures. While

Cited by 9

Thread Fork/Join Techniques for Multi-level Parallelism Exploitation

Xavier Martorell, Eduard Ayguadé, Nacho Navarro et al. · 1999

This paper presents some techniques for efficient thread forking and joining in parallel execution environments, taking into consideration the physical structure of NUMA machines and the support for multi-level parallelization and processor grouping. Two work generation schemes and one join mechanism are designed, implemented, evaluated and compared with the ones used in the IRIX MP library, an efficient implementation which supports a single level of parallelism. Supporting multiple levels of parallelism is a current research goal, both in shared and distributed memory machines. Our proposals include a first work generation scheme (GWD, or global work descriptor) which supports multiple levels of parallelism, but not processor grouping. The second work generation scheme (LWD, or local work descriptor) has been designed to support multiple levels of parallelism and processor grouping. Processor grouping is needed to distribute processors among different parts of the computation and maintain the working set of each processor across different parallel constructs. The mechanisms are evaluated using synthetic benchmarks, two SPEC95fp applications and one NAS application. The performance evaluation concludes that: i) the overhead of the proposed mechanisms is similar to the overhead of the existing ones when exploiting a single level of parallelism, and ii) a remarkable improvement in performance is obtained for applications that have multiple levels of parallelism. The comparison with the traditional single-level parallelism exploitation gives an improvement in the range of 30-65 % for these applications. 1.

Cited by 0

Exploiting Thread Level Parallelism by Loop Unrolling along Wavefronts

Johann Steinbrecher, Weijia Shang · Parallel and distributed computing and systems · 2012

In most previous work, loops are unrolled for optimizing the performance on single core architectures by reducing the loop overhead, exploiting instruction level parallelism or improving data locality.

Cited by 0

A Study of Thread Level Parallelism on Mobile Devices

2014

Abstract—Mobile devices continue to increase the number of cores in an attempt to meet the needs of performance-demanding applications. However, the increasing number of cores does not necessarily translate into performance gain and/or power reduction. In this paper we investigate how multi-core mobile devices are utilized by applications. Our results demonstrate that mobile applications are utilizing less than 2 cores on average, which shows that multi-cores are generally underutilized by today’s mobile applications. Unless application developers can significantly improve core utilization, further increasing core counts will result in little gain. I.

Cited by 0

Relational Profiling: Enabling Thread-Level Parallelism in Virtual Machines

2008

Virtual machine service threads can perform many tasks in parallel with program execution such as garbage collection, dynamic compilation, and profile collection and analysis. Hardware-assisted profiling is essential for providing service threads with needed information in a flexible and efficient way. A relational profiling architecture (RPA) is proposed for meeting this goal. The RPA selects particular instructions for profiling, and communicates collected information to service threads through shared memory message queues. The RPA’s capabilities lead to new profiling applications, such as concurrent garbage collection. Simulations indicate that a low-cost implementation of the RPA should be able to profile four in-flight instructions simultaneously, and provide storage for eight profile records. Profiling overhead is less than 0.5 % for concurrent garbage collection and edge profiling. 1

Cited by 0

An explicit parallelism study based on thread-level speculation

José Aguilar, Kahlil Campero · Greater South Information System · 2014

Developments in parallel architectures are an important branch in computer science. The success of such architectures derives from their inherent ability to improve the program performances. However, their ability to improve the performance on programs depends on the parallelism extraction strategies, which are always limited by the logic of each sequential program. Speculation is the only known alternative to overcome these constraints and increase the parallelism. In this paper, we study the explicit speculative parallelism using a library of thread-level speculation. We present the design of this library and study different speculative models: speculation of decision structures, speculation of loops, and speculation of critical sections. Our study evaluates different cases taken from SPEC CPU 2000, allowing acceleration of about 1.8x in multicore architectures (four core) with coarse-grained multithreaded.

Cited by 0Open access