Parallellisme en transputers
Koenraadt, APM · TU/e Research Portal (Eindhoven University of Technology) · 1987
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About 740 papers for “transputers”
Koenraadt, APM · TU/e Research Portal (Eindhoven University of Technology) · 1987
Cited by 0
Charles Leandro Hoher, Tiarajú Asmuz Diverio · Lume (Universidade Federal do Rio Grande do Sul) · 1996
Cited by 0Open access
Lang, K, Bristol Univ. (United Kingdom). Dept. of Aeronautical Engineers · OpenGrey (Institut de l'Information Scientifique et Technique) · 1985
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Cleverson Borges Sutil · Lume (Universidade Federal do Rio Grande do Sul) · 2014
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C.M. Onyango, J.A. Marchant, R.D. Tillett · 1994
Transputer networks coupled with hardware preprocessing modules, form an ideal platform for grading produce at high speed. The software design and the topology of the transputer network has been matched to the particular problem to increase the efficiency of the solution. The modular software structure reported includes facilities for transmitting data between modules and for providing timing, error reporting, and diagnostic functions. >
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Tony Hey · ePrints Soton (University of Southampton) · 1988
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David J. Pritchard · ePrints Soton (University of Southampton) · 1990
Cited by 39
Traian Muntean · 1988
Conception des supercalculateurs capables d'effectuer un grand nombre d'operations a la fois, en parallele sur des informations multiples. L'utilisation des transputers dans les supercalculateurs a reduit enormement le nombre d'interconnexions. Rappelons brievement qu'un transputer n'est plus ni moins qu'un ordinateur integre sur une seule puce, tout specialement concu, de surcroit, pour travailler en groupe
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A J G Hey, M Surridge, Jay Reeve · ePrints Soton (University of Southampton) · 1988
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Luigi Rizzo · CINECA IRIS Institutial research information system (University of Pisa) · 1992
Cited by 1
Tony Hey · ePrints Soton (University of Southampton) · 1987
Cited by 0
CERN · CERN Bulletin · 1989
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Stephen L. Christian · Concurrency Practice and Experience · 1991
Abstract This paper presents some of the work done at INMOS towards the development of a transputer‐based workstation to support its VLSI design community. The emphasis is on the practical application of multiple CPU technology to the solution of a specific problem and the advantages that transputers bring to such a system development. The more general use of transputer arrays for the acceleration of CAD algorithms is facilitated by the use of facilities within this workstation.
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C. P. H. Walker · 1996
Cited by 3
K. H. Shekhar, Y. N. Srikant · Computer Languages · 1993
Cited by 3
May, D, Thomson, P, Shepherd, R F · CERN Document Server (European Organization for Nuclear Research) · 1992
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José Fonseca, Gonçalves, Paulo J., A R Borges et al. · Portuguese National Funding Agency for Science, Research and Technology (RCAAP Project by FCT) · 1994
Neste artigo, é descrito um módulo multiprocessador baseado em transputers. Tem quatro processadores, cada qual com memória local, memória partilhada e interfaces a PC-AT e Ethernet. A proposta principal é a de construir um bloco (nó) com uma arquitectura message-passing de modo a evitar a interligação em malha 2-D. Foram tomados cuidados especiais para minimizar o número de chips envolvidos, bem como usadas as características especiais apresentadas pelo transputer no que diz respeito às comunicações interprocessador e concentrada toda a lógica de controlo num ASIC multifuncional. A especificação da placa, a análise racional do seu desenho e pin-out do ASIC estão apresentados e descritos em grande detalhe.
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Guy Lamarque, S. Gasnier · Signal Processing · 1992
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Franz J. Rammig · Journal of Microcomputer Applications · 1990
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Torsten Braun, Martina Zitterbart · 1991
High performance communication systems have to provide very high data rates of more than 100 Mbit/s to new applications such as multimedia applications. The bottleneck in communication systems is the protocol processing of the layers above media access control layer. Especially the transport and the network layer are very time consuming components of the protocol stack. To overcome this bottleneck light weight protocols such as XTP (Xpress Transfer Protocol) can be implemented on multiprocessor systems. XTP is a protocol with functionality of layers 3 and 4 and was designed for protocol processing in reliable high speed networks such as FDDI. XTP is based on several finite state machines to support an efficient implementation in VLSI. This paper presents a software implementation of XTP for a multiprocessor system. The implementation is based on these finite state machines, which are designed to run in parallel. The finite state machines are mapped onto processes, which can run in para...
Cited by 4