Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.
About 2,910 papers for “vector instructions”
Larsen, Samuel (Samuel Barton), 1975- · DSpace@MIT (Massachusetts Institute of Technology) · 2006
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Cited by 0Open access
Saman Amarasinghe, Rodric Rabbah, S. Larsen · DSpace@MIT (Massachusetts Institute of Technology) · 2009
Multimedia extensions are nearly ubiquitous in today's general-purpose processors. These extensions consist primarily of a set of short-vector instructions that apply the same opcode to a vector of operands. Vector instructions introduce a data-parallel component to processors that exploit instruction-level parallelism, and present an opportunity for increased performance. In fact, ignoring a processor's vector opcodes can leave a significant portion of the available resources unused. In order for software developers to find short-vector instructions generally useful, however, the compiler must target these extensions with complete transparency and consistent performance. This paper describes selective vectorization, a technique for balancing computation across a processor's scalar and vector units. Current approaches for targeting short-vector instructions directly adopt vectorizing technology first developed for supercomputers. Traditional vectorization, however, can lead to a performance degradation since it fails to account for a processor's scalar resources. We formulate selective vectorization in the context of software pipelining. Our approach creates software pipelines with shorter initiation intervals, and therefore, higher performance. A key aspect of selective vectorization is its ability to manage transfer of operands between vector and scalar instructions. Even when operand transfer is expensive, our technique is sufficiently sophisticated to achieve significant performance gains. We evaluate selective vectorization on a set of SPEC FP benchmarks. On a realistic VLIW processor model, the approach achieves whole-program speedups of up to 1.35x over existing approaches. For individual loops, it provides speedups of up to 1.75x.
Cited by 0Open access
Geoffrey Mainland, Roman Leshchinskiy, Simon Peyton Jones · ACM SIGPLAN Notices · 2013
Stream fusion is a powerful technique for automatically transforming high-level sequence-processing functions into efficient implementations. It has been used to great effect in Haskell libraries for manipulating byte arrays, Unicode text, and unboxed vectors. However, some operations, like vector append, still do not perform well within the standard stream fusion framework. Others, like SIMD computation using the SSE and AVX instructions available on modern x86 chips, do not seem to fit in the framework at all. In this paper we introduce generalized stream fusion, which solves these issues. The key insight is to bundle together multiple stream representations, each tuned for a particular class of stream consumer. We also describe a stream representation suited for efficient computation with SSE instructions. Our ideas are implemented in modified versions of the GHC compiler and vector library. Benchmarks show that high-level Haskell code written using our compiler and libraries can produce code that is faster than both compiler- and hand-vectorized C.
Cited by 0
Valentin Le Fèvre, Marc Casas · arXiv (Cornell University) · 2023
The Sparse GEneral Matrix-Matrix multiplication (SpGEMM) $C = A \times B$ is a fundamental routine extensively used in domains like machine learning or graph analytics. Despite its relevance, the efficient execution of SpGEMM on vector architectures is a relatively unexplored topic. The most recent algorithm to run SpGEMM on these architectures is based on the SParse Accumulator (SPA) approach, and it is relatively efficient for sparse matrices featuring several tens of non-zero coefficients per column as it computes C columns one by one. However, when dealing with matrices containing just a few non-zero coefficients per column, the state-of-the-art algorithm is not able to fully exploit long vector architectures when computing the SpGEMM kernel. To overcome this issue we propose the SPA paRallel with Sorting (SPARS) algorithm, which computes in parallel several C columns among other optimizations, and the HASH algorithm, which uses dynamically sized hash tables to store intermediate output values. To combine the efficiency of SPA for relatively dense matrix blocks with the high performance that SPARS and HASH deliver for very sparse matrix blocks we propose H-SPA(t) and H-HASH(t), which dynamically switch between different algorithms. H-SPA(t) and H-HASH(t) obtain 1.24$\times$ and 1.57$\times$ average speed-ups with respect to SPA respectively, over a set of 40 sparse matrices obtained from the SuiteSparse Matrix Collection. For the 22 most sparse matrices, H-SPA(t) and H-HASH(t) deliver 1.42$\times$ and 1.99$\times$ average speed-ups respectively.
Cited by 0Open access
Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu et al. · 2019
Vector gather instructions are responsible for handling indirect memory accesses in vector processing. Since the indirect memory accesses usually express irregular access patterns, they have relatively low spatial and temporal locality compared with regular access patterns. As a result, an application with many vector gather instructions suffers from long latencies of the indirect memory accesses. Thus, the long latencies cause a significant performance degradation in vector processing. This paper proposes a hardware prefetching mechanism to hide memory access latencies of indirect memory accesses. The mechanism prefetches cacheable index data before executing a vector gather instruction, and predicts the addresses of the memory requests issued by the vector gather instruction. The mechanism then tries to prefetch the data based on the predicted addresses. As a result, the mechanism can reduce the memory access latencies of vector gather instructions. Moreover, this paper discusses how many cache blocks should be loaded per prediction regarding a single vector gather instruction by varying the prefetching parameters of distance and degree. In the evaluation, the performance of a simple kernel is examined with two types of index data: sequential and random. The evaluation results show that the prefetching mechanism improves the performance of the sequential-indexed and random-indexed kernels by 2.2x and 1.2x, respectively.
Cited by 3
B Kavyashree, A Geethashree, Suresh Muthusamy et al. · 2025
This research aims to enhance the performance of RISC-V's vector extension by optimizing load and store operations, critical for efficient parallel processing in applications like multimedia and high-performance computing. The proposed design introduces a pipelined architecture with three execution stages: Instruction Decision-Instruction Work (ID-IE), Instruction Work-Data Memory (IE-DM), and Data Memory-Write-Back (DM-WB). These stages address memory bandwidth and latency challenges, improving data transfer efficiency between vector registers and memory. Implemented using ASIC, the design is evaluated for area, power, and processing performance. Complexity is analyzed through pipeline stage interactions, and computational cost is assessed via simulation metrics. Effectiveness is measured by comparing throughput and latency against baseline RISC-V implementations. This work advances RISC-V's scalability for data-intensive tasks, ensuring compliance with vector extension standards.
Cited by 0
Akter, Mamtaj · Scholars' Bank (University of Oregon) · 2020
The Basic Linear Algebra Subprograms or BLAS provide the foundation\n\nfor much of the software used in scientific computing. To date, BLAS has been\n\nimplemented in C, Fortran, and directly in assembly. These languages allow the\n\nimplementations to be well optimized by hand ensuring when a BLAS routine is\n\ncalled that it is as fast a possible.\n\nFunctional programming languages, and in particular Haskell, do not allow\n\nthe fine-grained control over memory, and their high-level features make it hard\n\nto optimize a single function to the level of C or assembly. However, Haskell\n\nhas an advantage when optimizing combinations of container-based operations.\n\nBecause of this we explore both implementing BLAS in Haskell and comparing the\n\nGlasgow Haskell Compiler’s ability to optimize scientific programs to that of a C\n\ncompiler.
Cited by 0Open access
H. Cheng, Johann Großschädl, Jiatong Tian et al. · Zenodo (CERN European Organization for Nuclear Research) · 2020
Single-Instruction-Multiple-Data (SIMD) extensions like Intel's AVX2 o er a great potential to accelerate elliptic curve cryptography compared to a straightforward implementation using only base x64 instructions. All existing AVX2 implementations of scalar multiplication on Curve25519 and alternative elliptic curves are optimized for low latency. We argue in this paper that many applications, most notably server-side TLS handshake processing, would bene t more from throughput-optimized implementations than latency-optimized ones. To support this argument we introduce throughput-optimized AVX2 implementations of variable-base scalar multiplication on Curve25519 and xed-base scalar multiplication on Ed25519. Both implementations perform four scalar multiplications in parallel, whereby each scalar multiplication uses a 64-bit element of a 256-bit AVX2 vector. The eld arithmetic is based on a radix-229 representation of the eld elements, which makes it possible to execute four parallel multiplications modulo a multiple of p = 2255 19 in just 88 Skylake cycles. Four variable-base scalar multiplications on Curve25519 require less than 250,000 Skylake cycles, which translates into a throughput of 32,318 scalar multiplications per second at a clock frequency of 2 GHz. For comparison, the currently best latency-optimized AVX2 implementation reaches a throughput of only about 21,000 scalar multiplications per second on the same Skylake processor.
Cited by 2Open access
Robert Ramstad · ResearchWorks at the University of Washington (University of Washington) · 2024
Thesis (Master's)--University of Washington, 2024
Cited by 0Open access
Cambridge England, Roman Leshchinskiy, Simon Peyton Jones · 2014
Stream fusion [6] is a powerful technique for automatically transforming high-level sequence-processing functions into efficient implementations. It has been used to great effect in Haskell libraries for manipulating byte arrays, Unicode text, and unboxed vectors. However, some operations, like vector append, still do not perform well within the standard stream fusion framework. Others, like SIMD computation using the SSE and AVX instructions available on modern x86 chips, do not seem to fit in the framework at all. In this paper we introduce generalized stream fusion, which solves these issues. The key insight is to bundle together multiple stream representations, each tuned for a particular class of stream consumer. We also describe a stream representation suited for efficient computation with SSE instructions. Our ideas are implemented in modified versions of the GHC compiler and vector library. Benchmarks show that high-level Haskell code written using our compiler and libraries can produce code that is faster than both compiler- and hand-vectorized C. D.3.3 [Software]: Program-
Cited by 0
Sreeharsha Udayashankar, Abdelrahman Baba, Samer Al-Kiswany · ArXiv.org · 2025
Content-defined Chunking (CDC) algorithms dictate the overall space savings that deduplication systems achieve. However, due to their need to scan each file in its entirety, they are slow and often the main performance bottleneck within data deduplication. We present VectorCDC, a method to accelerate hashless CDC algorithms using vector CPU instructions, such as SSE / AVX. We analyzed the state-of-the-art chunking algorithms and discovered that hashless algorithms primarily use two data processing patterns to identify chunk boundaries: Extreme Byte Searches and Range Scans. VectorCDC presents a vector-friendly approach to accelerate these two patterns. Using VectorCDC, we accelerated three state-of-the-art hashless chunking algorithms: RAM, AE, and MAXP. Our evaluation shows that VectorCDC is effective on Intel, AMD, ARM, and IBM CPUs, achieving 8.35x - 26.2x higher throughput than existing vector-accelerated algorithms, and 15.3x - 207.2x higher throughput than existing unaccelerated algorithms. VectorCDC achieves this without affecting the deduplication space savings.
Cited by 0Open access
Sreeharsha Udayashankar, Abdelrahman Baba, Samer Al-Kiswany · ACM Transactions on Storage · 2026
Content-defined Chunking (CDC) algorithms dictate the overall space savings that deduplication systems achieve. However, due to their need to scan each file in its entirety, they are slow and often the main performance bottleneck within data deduplication. We present VectorCDC, a method to accelerate hashless CDC algorithms using vector CPU instructions, such as SSE / AVX. We analyzed the state-of-the-art chunking algorithms and discovered that hashless algorithms primarily use two data processing patterns to identify chunk boundaries: Extreme Byte Searches and Range Scans . VectorCDC presents a vector-friendly approach to accelerate these two patterns. Using VectorCDC, we accelerated three state-of-the-art hashless chunking algorithms: RAM, AE, and MAXP. Our evaluation shows that VectorCDC is effective on Intel, AMD, ARM, and IBM CPUs, achieving 8.35 × –26.2 × higher throughput than existing vector-accelerated algorithms, and 15.3 × –207.2 × higher throughput than existing unaccelerated algorithms. VectorCDC achieves this without affecting the deduplication space savings.
Cited by 0Open access
Ling Yang, Mengyang Xu, Weimao Ke · arXiv (Cornell University) · 2024
Question-answering (QA) is an important application of Information Retrieval (IR) and language models, and the latest trend is toward pre-trained large neural networks with embedding parameters. Augmenting QA performances with these LLMs requires intensive computational resources for fine-tuning. We propose an innovative approach to improve QA task performances by integrating optimized vector retrievals and instruction methodologies. Based on retrieval augmentation, the process involves document embedding, vector retrieval, and context construction for optimal QA results. We experiment with different combinations of text segmentation techniques and similarity functions, and analyze their impacts on QA performances. Results show that the model with a small chunk size of 100 without any overlap of the chunks achieves the best result and outperforms the models based on semantic segmentation using sentences. We discuss related QA examples and offer insight into how model performances are improved within the two-stage framework.
Cited by 0Open access
Jarosław Bilski, Bartosz Kowalczyk · Lecture notes in computer science · 2025
Cited by 0
Armando Faz-Hernández, Julio López, Ricardo Dahab · ACM Transactions on Mathematical Software · 2019
Elliptic curve cryptosystems are considered an efficient alternative to conventional systems such as DSA and RSA. Recently, Montgomery and Edwards elliptic curves have been used to implement cryptosystems. In particular, the elliptic curves Curve25519 and Curve448 were used for instantiating Diffie-Hellman protocols named X25519 and X448. Mapping these curves to twisted Edwards curves allowed deriving two new signature instances, called Ed25519 and Ed448, of the Edwards Digital Signature Algorithm. In this work, we focus on the secure and efficient software implementation of these algorithms using SIMD parallel processing. We present software techniques that target the Intel AVX2 vector instruction set for accelerating prime field arithmetic and elliptic curve operations. Our contributions result in a high-performance software library for AVX2-ready processors. For example, our library computes digital signatures 19% (for Ed25519) and 29% (for Ed448) faster than previous optimized implementations. Also, our library improves by 10% and 20% the execution time of X25519 and X448, respectively.
Cited by 39Open access
Sungchul Han, Sukchan Kang · 2008
In this paper, we present a vectorized version of the Floyd-Warshall shortest-path algorithm to improve the performance. The vectorized implementation utilizes the single instruction multiple data (SIMD) instructions available in Intel architectures. The experimental results show that the instructionlevel parallelism obtained by simultaneously processing 8 nodes combined with unrolling yields between 2.3 and 5.2 times of speed-up over the existing blocking algorithms, which only utilize cache locality.
Cited by 0
Hikaru Takayashiki, Masayuki Satō, Kazuhiko Komatsu et al. · 2022
Vector gather instructions are available in various processors, which are essential for handling irregular memory accesses. Additionally, the processors support virtual memory that allows programmers not to consider the limitation of the physical memory space. To realize the virtual memory, the processors require address translation between virtual and physical addresses. When a vector gather instruction loads data elements distributed over the physical memory space, all virtual addresses must be translated one by one, causing many translations by accessing a Translation Lookaside Buffer (TLB). Hence, the TLB easily becomes a bottleneck in handling vector gather instructions. To relieve the bottleneck, this paper proposes an address coalescing method for the address translations of vector gather instructions by utilizing vector arithmetic units in the processor. The evaluation results show that the proposed method can achieve a 2x performance improvement in numerical and 1.08x in graph applications, which contain many vector gather instructions.
Cited by 0
Xianqin Li, Liang Liu, Dejian Li et al. · 2023
Verifying the instruction execution against a golden execution model following the ISA is becoming a common practice to verify processors. This method plays an important role in the single-core verification scenario. However, for the correctness monitoring of multi-core processors, the uncertainty caused by shared storage makes the above method unable to meet the requirements better. This paper provides a multi-core function verification scheme of vector instructions based on RISC-V architecture, which monitors the instruction execution time of DUT and triggers the reference model in time through Test Bench. This scheme uses Spike, the instruction set standard implementation model specified by RISC-V Foundation, as the reference model of verification environment. It adds a DPI (Direct Programming Interface) interface for the simulation environment to call, modifies the execution mechanism of vector instructions in Spike's existing model, and then triggers the synchronous execution of Spike with the time of the instruction monitored from each core in the DUT (design under test), and finally compares the execution results of the DUT and Spike. From the top level, although there is no adjudication mechanism for the order of multi-core access data in Spike, the time of data acquisition or update of each core is exactly the same as that in the DUT. So that the multi-core comparison verification of vector instructions can be completed in the simulation stage, and more bugs such as vector instructions and multi-core consistency can be found earlier.
Cited by 0
Yixuan Mei, S Varshini, Harish Dattatraya Dixit et al. · 2026
Silent Data Corruption (SDC) poses a reliability threat in modern datacenters. These insidious errors evade detections and propagate incorrect results throughout the system. Companies including Google, Meta, and Alibaba have reported SDC incidents affecting their production. In this paper, we present the first comprehensive instruction- and application-level analysis of vector instruction SDCs in hyper-scale datacenters using a two-stage approach. We perform over 78 trillion test rounds in more than 14 billion CPU seconds. Our observations reveal undocumented SDC patterns that provide insights into possible underlying causes and inspire new mitigation strategies. Based on these findings, we propose a low-overhead SDC detection mechanism leveraging in-application algorithm-based fault tolerance. Our method achieves 88% to 100% SDC machine detection rate with a time overhead of only 1.35% even for modestly sized inputs.
Cited by 0Open access
Xudong Wang, James Lin, Qiucheng Liao · 2023
We investigated the performance impact of IEEE-754 double-precision floating-point subnormal numbers, focusing on vector arithmetic and transcendental functions across Intel, AMD, and HiSilicon CPUs. We developed a benchmark tool, SNBench, and uncovered that subnormal numbers can extend instruction latency and reciprocal throughput by up to 162 cycles on Intel, 13 cycles on AMD, and 2 cycles on HiSilicon processors. The impact is more pronounced in transcendental functions, with performance losses reaching up to 562 cycles on Intel, 404 cycles on AMD, and 62 cycles on HiSilicon CPUs.
Cited by 0