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About 2,492 papers for “vector processors”

Vector Network Processors

Madhusudanan Seshadri · 2002

The need for programmability and in-the-field upgradeability has resulted in network processors replacing fixed function ASICs in the market for network routers and switches. Network processors were the fastest growing segment of the microprocessor industry in 2000 and revenues are expected to increase at a compound annual growth rate of nearly 63 % [1]. Network processors being developed today show

Cited by 0

Arithmetic for vector processors

R. Kirchner, Ulrich Kulisch · 1987

In electronic computers the elementary-arithmetic operations are these days generally approximated by floating-point operations of highest accuracy. Vector processors and parallel computers often provide additional operations like “multiply and add”, “accumulate” or “multiply and accumulate”. Also these operations shall always deliver the correct answer whatever the data are. The user should not be oblighed to execute an error analysis for operations predefined by the manufacturer. In the first part of this paper we discuss circuits which allow a fast and correct computation of sums and scalar products making use of a matrix shaped arrangement of adders and pipeline technology. In the second part a variant is discussed which permits a drastic reduction in the number of adders required. The methods discussed in this paper can also be used to build a fast arithmetic unit for micro computers in VLSI-technology.

Cited by 18

Multithreading in vector processors

Constantinos Evangelinos · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Cited by 0Open access

Cache performance of vector processors

Kimming So, V. Zecca · ACM SIGARCH Computer Architecture News · 1988

An instruction-level simulator for IBM 3090 with VF (vector facility) has been developed for studying the performance of vector processors and their memory hierarchies. Initial use of the simulator is to understand the program locality of real vectorized applications. Observation on several large scientific applications indicates that the program locality of vector execution can be significantly different from that of the scalar execution of the same application. Although these large applications generally do not exhibit a locality as strong as that of the conventional mainframe applications, their cache hit ratios are high enough to take advantage of a cache. The cache performance of these applications with respect to various cache parameters is also presented.

Cited by 26

Logic simulation on vector processors

R. Raghavan, John P. Hayes, William R. Martin · 2003

The performance of three commercial vector computers, the Cray X-MP/48, IBM 3090/400, and Alliant FX/8, for simulating logic circuits at gate level is compared. Experiments that assume zero- and unit-delay models demonstrate that certain key architectural features, especially, the presence of a scalar cache, have an adverse impact on the potential speedup. Consequently, the achievable speedup due to vectorization of simulation code, while still substantial, is less than expected. The results indicate that concurrent operation of multiple CPUs in vector mode in machines such as the Alliant FX/8 might be the most cost-effective speedup technique for logic simulation on current vector processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 21

Circuit simulation on vector processors

Andrei Vladimirescu, D.O. Pederson · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1982

Vector computers have an increased potential for fast, accurate simulation at the transistor level of circuits. Design considerations for a new circuit simulator are developed based on the specifics of the vector computer architecture and of LSI circuits. The performance of the new LSI simulator, CLASSIE, is evaluated on a Cray-1 vector-computer for several circuits with from a few hundred to over one thousand semiconductor devices. Comments are given concerning the performance limits and relative hardware dependence. 6 references.

Cited by 19

FPGA-Based Soft Vector Processors

Peter Yiannacouras · TSpace (University of Toronto) · 2009

FPGAs are increasingly used to implement embedded digital systems because of their low time-to-market and low costs compared to integrated circuit design, as well as their superior performance and area over a general purpose microprocessor. However, the hardware design necessary to achieve this superior performance and area is very difficult to perform causing long design times and preventing wide-spread adoption of FPGA technology. The amount of hardware design can be reduced by employing a microprocessor for less-critical computation in the system. Often this microprocessor is implemented using the FPGA reprogrammable fabric as a soft processor which can preserve the benefits of a single-chip FPGA solution without specializing the device with dedicated hard processors. Current soft processors have simple architectures that provide performance adequate for only the least-critical computations. &#13;\nOur goal is to improve soft processors by scaling their performance and expanding their suitability to more critical computation. To this end we focus on the data parallelism found in many embedded applications and propose that soft processors be augmented with vector extensions to exploit this parallelism. We support this proposal through experimentation with a parameterized soft vector processor called VESPA (Vector Extended Soft Processor Architecture) which is designed, implemented, and evaluated on real FPGA hardware. &#13;\nThe scalability of VESPA combined with several other architectural parameters can be used to finely span a large design space and derive a custom architecture for exactly matching the needs of an application. Such customization is a key advantage for soft processors since their architectures can be easily reconfigured by the end-user. Specifically, customizations can be made to the pipeline, functional units, and memory system within VESPA. In addition, general purpose overheads can be automatically eliminated from VESPA. &#13;\nComparing VESPA to manual hardware design, we observe a 13x speed advantage for hardware over our fastest VESPA, though this is significantly less than the 500x speed advantage over scalar soft processors. The performance-per-area of VESPA is also observed to be significantly higher than a scalar soft processor suggesting that the addition of vector extensions makes more efficient use of silicon area for data parallel workloads.

Cited by 5Open access

Pseudo-Random Number Generators for Vector Processors and Multicore Processors

Agner Fog · Journal of Modern Applied Statistical Methods · 2015

Large scale Monte Carlo applications need a good pseudo-random number generator capable of utilizing both the vector processing capabilities and multiprocessing capabilities of modern computers in order to get the maximum performance. The requirements for such a generator are discussed. New ways of avoiding overlapping subsequences by combining two generators are proposed. Some fundamental philosophical problems in proving independence of random streams are discussed. Remedies for hitherto ignored quantization errors are offered. An open source C++ implementation is provided for a generator that meets these needs.

Cited by 12Open access

Dual Vector Load for Improved Pipelining in Vector Processors

Viktor Razilov, Juncen Zhong, Emil Matúš et al. · 2023

Vector processors execute instructions that manipulate vectors of data items using time-division multiplexing (TDM). Chaining, the pipelined execution of vector instruction, ensures high performance and utilization. When two vectors are loaded sequentially to be the input of a follow-up compute instruction, which is often the case in vector applications, chaining cannot take effect during the duration of the entire first vector load. To close this gap, we propose dual load: A parallel or interleaved load of the two input vectors. We study this feature analytically and make statements on necessary conditions for performance improvements. Our investigation finds that compute-bound and some memory-bound applications profit from this feature when the memory and compute bandwidths are sufficiently high. A speedup of up to 33 % is possible in the ideal case. Our practical implementation shows improvements of up to 21 % with a hardware overhead of less than 2 %.

Cited by 1

Optimisation For Vector And Risc Processors

M. Ashworth · 1998

Single node performance is a key issue in the optimisation of codes for massively parallel processors, especially for applications like ocean and atmospheric modelling where high parallel efficiency is easily obtained from the natural data locality. In this paper we demonstrate how specific optimisations to suit a particular target processor architecture can give significant performance benefits for a shallow sea model running on a range of high performance systems. A benchmark performance comparison between code optimised for vector processors and for scalar, cache-based processors shows a performance gain of up to a factor of 8.3 between the better and worse performing code. We also highlight the problems of maintaining a portable code that will perform well on both scalar and vector processors. 1. Introduction It is now possible for most scientific codes to achieve high parallel efficiency on today&amp;apos;s high performance computer (HPC) systems, whether it is by using shared m...

Cited by 0

Impact of vector processors on algorithms

B.L. Buzbee, Andrew McKnight · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1979

New computer architectures such as the STAR 100, Cray-1, and other vector and parallel processors have had considerable impact on algorithm construction. Significant gains can be obtained from intensive mathematical analysis of an algorithm used in specific tasks, for example, the order of nesting DO loops. One such example that has wide application in computational physics is the diffusion problem addressed in this paper.

Cited by 0Open access

Memory access reordering in vector processors

De-Lei Lee · 2002

Interference among multiple vector streams that access memory concurrently is the major source of performance degradation in main memory of pipelined vector processors. While totally eliminating interference appears to be impossible, little is known on how to design a memory system that can reduce it. In this paper, we introduce a concept called memory access reordering for reducing interference. This technique reduces interference by means of making the multiple vector streams access memory in an orderly fashion. Effective algorithms for memory access reordering are presented and their efficient hardware implementations are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 4