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article · 1985

A 42ps 2K-gate GaAs gate array

Nagaoki Toyoda, Naotaka Uchitomi, Y. Kitaura, M. Mochizuki, K. Kanazawa, Tomoki P. Terada, Y. Ikawa, A. Hojo

Cited by 11Abstract and details only

Abstract

TO INCREASE speed of microelectronic systems, it is the inter-chip signal delay that should be reduced by maximizing the integration level. As the integration level increases, however, the development time becomes longer. The rapid development of LSIs is increasingly important because the product life cycle has been becoming shorter. A

Cite this paper

APA 7

Toyoda, N., Uchitomi, N., Kitaura, Y., Mochizuki, M., Kanazawa, K., Terada, T. P., Ikawa, Y., & Hojo, A. (1985). A 42ps 2K-gate GaAs gate array. https://doi.org/10.1109/isscc.1985.1156841

MLA 9

Toyoda, Nagaoki, et al. “A 42ps 2K-gate GaAs gate array.” vol. sc 18, 1985, pp. 206–07, https://doi.org/10.1109/isscc.1985.1156841.

Chicago

Toyoda, Nagaoki, Naotaka Uchitomi, Y. Kitaura, M. Mochizuki, K. Kanazawa, Tomoki P. Terada, Y. Ikawa, and A. Hojo. 1985. “A 42ps 2K-gate GaAs gate array.” https://doi.org/10.1109/isscc.1985.1156841.

Harvard

Toyoda, N. et al. (1985) ‘A 42ps 2K-gate GaAs gate array’. Available at: https://doi.org/10.1109/isscc.1985.1156841.

BibTeX
@article{toyoda198542ps,
  title = {{A 42ps 2K-gate GaAs gate array}},
  author = {Toyoda, Nagaoki and Uchitomi, Naotaka and Kitaura, Y. and Mochizuki, M. and Kanazawa, K. and Terada, Tomoki P. and Ikawa, Y. and Hojo, A.},
  volume = {sc 18},
  pages = {206--207},
  year = {1985},
  doi = {10.1109/isscc.1985.1156841}
}

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