article · 2012

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh‐Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu

Cited by 2Abstract and details only

Abstract

We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V TH ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V TH measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to -45°C, and post-layout simulations show the resolution of the digital read-out scheme is <;60; 0.2mV per bit. Measured V TH distributions agree well with Monte Carlo simulation results.

Cite this paper

APA 7

Lin, G.-C., Wang, S.-C., Lin, Y.-W., Tsai, M.-C., Chuang, C.-T., Jou, S., Lien, N.-C., Shih, W.-C., Lee, K.-D., & Chu, J.-K. (2012). An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. https://doi.org/10.1109/iscas.2012.6271804

MLA 9

Lin, Geng-Cing, et al. “An all-digital bit transistor characterization scheme for CMOS 6T SRAM array.” 2012, pp. 2485–88, https://doi.org/10.1109/iscas.2012.6271804.

Chicago

Lin, Geng-Cing, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh‐Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, and Jyun-Kai Chu. 2012. “An all-digital bit transistor characterization scheme for CMOS 6T SRAM array.” https://doi.org/10.1109/iscas.2012.6271804.

Harvard

Lin, G.-C. et al. (2012) ‘An all-digital bit transistor characterization scheme for CMOS 6T SRAM array’. Available at: https://doi.org/10.1109/iscas.2012.6271804.

BibTeX

@article{lin2012digital,
  title = {{An all-digital bit transistor characterization scheme for CMOS 6T SRAM array}},
  author = {Lin, Geng-Cing and Wang, Shao-Cheng and Lin, Yi-Wei and Tsai, Ming-Chien and Chuang, Ching-Te and Jou, Shyh‐Jye and Lien, Nan-Chun and Shih, Wei-Chiang and Lee, Kuen-Di and Chu, Jyun-Kai},
  pages = {2485--2488},
  year = {2012},
  doi = {10.1109/iscas.2012.6271804}
}

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