????????? · The Royal Society of Chemistry’s Journals, Books and Databases (The Royal Society of Chemistry) · 2010
In this paper, a low-power UWB CMOS LNA is designed by using a common-gate (CG) amplifier, folded cascode amplifier, and current-reused techniques. A CG amplifier is utilized at the first stage for wideband input matching. At the second stage, a folded cascode amplifier with current-reused technique is used to obtain a high power gain. In addition, for a wide bandwidth, splitting-load inductive peaking and series inductive peaking techniques are employed. The proposed LNA has a maximum power gain of 13.14 ???, a minimum noise figure of 3.45 ???, and 3-??? bandwidth from 3.98 to 9.35 ??? while consuming 12.8 ??? from 1 V.
Cited by 0
Saburo Muroga · 2003
Cited by 0
R. Jacob Baker · 2008
Cited by 74
2008
Cited by 0
Michiel Steyaert, P. Vancorenland · Proceedings - ACM IEEE Design Automation Conference · 2002
An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low costs, both in the CMOS technology as well as the power.
Cited by 0
Purdue E-pubs, Ik Joon Chang, Ik Joon Chang et al. · 2008
Cited by 0
Reynolds, Robert G., Collar, David C., Pasachnik, Stesha A. et al. · DRYAD · 2016
Cited by 0Open access
T. Gabara · 2002
Low power dissipation using conventional CMOS circuits can be achieved if the power supply lead is ramped repetitively between VDD and VSS. During the power-down edge, the state of the chip is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (Pulsed Power Supply) CMOS and reduces the power dissipation over conventional 0.9 /spl mu/m p/sup +/ epi CMOS by 10 X.
Cited by 12
Mike Mayberry · 2007
This article consists of a collection of slides from the author's conference presentation on the future of CMOS technologies. Some of the specific topics discussed include: the market for CMOS scaling; design considerations for materials plus CMOS scaling; the future that considers devices plus materials plus CMOS scaling; and new areas of future chip development.
Cited by 0
Salvador, João Manuel Lameiras · Universidade Nova de Lisboa's Repository (Universidade Nova de Lisboa) · 2023
Cryptography, the science of secure communication, plays an essential role in safeguarding sensitive information, preserving privacy, and ensuring the integrity of digital communications. Among the various cryptographic components, Random Number Generators (RNGs) are es- sential to maintain the robustness of a cryptographic system. They generate unpredictable and uniformly distributed random values, that are essential for generating cryptographic keys. There are two kinds of random number generators, the True Random Number Generators (TRNGs) and the Pseudo Random Number Generators (PRNGs). PRNGs use an initial seed to produce random numbers using a deterministic algorithm, meaning that if an opponent finds the initial seed it can easily reproduce the cryptographic key and compromise the security of that confidential information. TRNGs generate random numbers through unpredictable physical processes, ensuring genuine randomness for cryptographic applications, increasing the security. This solves the problem of PRNGs previously mentioned. The objective of this work is to develop a TRNG that uses jitter created by a ring oscil- lator, as the source of randomness, using a 130-nanometer semiconductor process. Compared with the current state-of-the-art TRNGs, the proposed TRNG showed better or comparable results in throughput, achieving a rate of 52.3Mb/s, occupied a mere 3854 μ2 in terms of area, demonstrated resilience against temperature and supply voltage fluctuations. These characteristics were achieved by the multiple current starved ring oscillators that can provide 500 ps of jitter. Nonetheless, its performance in power efficiency was disappointing, consuming 1.029mW.
Cited by 0Open access
Mohanty, Saraju P, Srivastava, Ashok · CERN Document Server (European Organization for Nuclear Research) · 2016
Over two volumes this work describes the modelling, design, and implementation of nano-scaled CMOS electronics, and the new generation of post-CMOS devices, at both the device and circuit levels.
Cited by 0
Nor Zaidi Haron, Said Hamdioui · 2010
CMOS/Molecular (CMOL) memory is one of the emerging memory technologies that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS-based peripheral circuits. Similarly to existing 3D technology, vertical vias are utilized to connect the two components. Because of their critical location and small in size, these CMOS to Non-CMOS Vias (CNVs) are prone to fabrication imperfection. A defective CNV may cause inaccessibility to the memory cell array, which in turn decreases the overall yield and/or reliability. This paper presents a modified CMOL architecture that mitigates faults due to defective CNVs. It is based on combining the Redundant Residue Number System (RRNS) error correction code (ECC) and interleaving. The number of banks interleaved in CMOL memories is determined by the ECC capability. Simulation results show that by setting an appropriate ECC capability with the associated number of banks, 95% to 100% mitigation of defective CNVs can be realized.
Cited by 1
Valeria Bragaglia · 2023
Backend - CMOS Compatible Devices for Beyond CMOSValeria Bragaglia aa IBM Research Europe — Zurich, CH-8803 Rüschlikon, SwitzerlandProceedings of Neuronics Conference (Neuronics)València, Spain, 2024 February 21st - 23rdOrganizers: Sabina Spiga and Juan BisquertInvited Speaker, Valeria Bragaglia, presentation 023DOI: https://doi.org/10.29363/nanoge.neuronics.2024.023Publication date: 18th December 2023The growing demand for data-driven applications in every layer of society results in traditional von-Neumann architecture with disjoint memory and processing to be at its limit, as it suffers from huge memory latency and limited data bandwidth, which is further intensified by the scaling limits of silicon transistors. A new roadmap for beyond CMOS is under discussion and this is driving interest in utilizing unique characteristics of emerging devices for information processing and memory[1]. One of the challenges is to identify emerging devices that can implement computing functions and architectures more efficiently than CMOS and Boolean logic. Neuro-inspired chips that mimic the behavior and the efficiency of biological networks of neurons and synapses are receiving particular attention, as most of the AI related problems rely on neural network mathematical models. Reducing data movement and parallelizing vector matrix multiplications are key aspects in establishing more energy-efficient AI hardware. Device technologies based on metal-oxide HfO2 and VO2, as well as phase change memories (PCM) based on GeSbTe and Sb2Te3 are perfect candidates for the realization of synapse and neuronal functions in these artificial neural networks. In this talk I will give an overview on our approach to accelerate deep neural networks for inference and training applications using Resistive Random-Access Memories (ReRAM)[2] and PCM[3], as well as on the use of oscillating neural networks based on VO2 oscillators for solving optimization problems[4]. References:[1] The International Roadmap for devices and systems 2022 by IEEE[2] N. Gong et al. "Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization," IEDM 2022[3] M. Le Gallo et al., "A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference," Nature Electronics, 6, 680–693, 2023[4] G. Csaba and W. Porod, "Coupled oscillators for computing: A review and perspective," Applied Physics Review, 7, 011302, 2020© FUNDACIO DE LA COMUNITAT VALENCIANA SCITOnanoGe is a prestigious brand of successful science conferences that are developed along the year in different areas of the world since 2009. Our worldwide conferences cover cutting-edge materials topics like perovskite solar cells, photovoltaics, optoelectronics, solar fuel conversion, surface science, catalysis and two-dimensional materials, among many others.nanoGe Fall MeetingnanoGe Fall Meeting (NFM) is a multiple symposia conference celebrated yearly and focused on a broad set of topics of advanced materials preparation, their fundamental properties, and their applications, in fields such as renewable energy, photovoltaics, lighting, semiconductor quantum dots, 2-D materials synthesis, charge carriers dynamics, microscopy and spectroscopy semiconductors fundamentals, etc.nanoGe Spring MeetingThis conference is a unique series of symposia focused on advanced materials preparation and fundamental properties and their applications, in fields such as renewable energy (photovoltaics, batteries), lighting, semiconductor quantum dots, 2-D materials synthesis and semiconductors fundamentals, bioimaging, etc.International Conference on Hybrid and Organic PhotovoltaicsInternational Conference on Hybrid and Organic Photovoltaics (HOPV) is celebrated yearly in May. The main topics are the development, function and modeling of materials and devices for hybrid and organic solar cells. The field is now dominated by perovskite solar cells but also other hybrid technologies, as organic solar cells, quantum dot solar cells, and dye-sensitized solar cells and their integration into devices for photoelectrochemical solar fuel production.Asia-Pacific International Conference on Perovskite, Organic Photovoltaics and OptoelectronicsThe main topics of the Asia-Pacific International Conference on Perovskite, Organic Photovoltaics and Optoelectronics (IPEROP) are discussed every year in Asia-Pacific for gathering the recent advances in the fields of material preparation, modeling and fabrication of perovskite and hybrid and organic materials. Photovoltaic devices are analyzed from fundamental physics and materials properties to a broad set of applications. The conference also covers the developments of perovskite optoelectronics, including light-emitting diodes, lasers, optical devices, nanophotonics, nonlinear optical properties, colloidal nanostructures, photophysics and light-matter coupling.International Conference on Perovskite Thin Film Photovoltaics Perovskite Photonics and OptoelectronicsThe International Conference on Perovskite Thin Film Photovoltaics Perovskite Photonics and Optoelectronics (NIPHO) is the best place to hear the latest developments in perovskite solar cells as well as on recent advances in the fields of perovskite light-emitting diodes, lasers, optical devices, nanophotonics, nonlinear optical properties, colloidal nanostructures, photophysics and light-matter coupling.
Cited by 0
2016
Cited by 0
S.D.S. Malhi, K.E. Bean, R. Sunderesan et al. · Electronics Letters · 1986
A CMOS structure where the source and drain terminals of the MOSFETs are in polysilicon overlaid on top of a thick oxide and the channel is in single-crystal silicon is described, utilising a 970°C SiH4 CVD process which simultaneously deposits epitaxial silicon on the exposed silicon substrate and polysilicon on oxide. The structure allows a more compact CMOS inverter layout and reduced source/drain parasitic capacitances.
Cited by 1
Rajeev J. Ram, Jin Xue · 2022
Silicon technologies have been developed for both electronics and photonics. Future demands call for further innovation in each field separately, but also depend on our ability to bring the best of both worlds together through integrated solutions. For decades, the pursuit of all-silicon electronic-photonic integration has been hindered by the lack of a native light source due to silicon's indirect bandgap. Here, we discuss the potential for micro- and nano-scale light sources realized in microelectronic CMOS technology without any modification or postprocessing. High brightness is realized by exploiting the well-passivated silicon surfaces available in CMOS to realize efficient light emission despite the indirect bandgap. NIR emission at the silicon bandgap is demonstrated and exploited to demonstrate chip-to-chip optical links and sensors utilizing only silicon light sources.
Cited by 0
Helen Merina Albert, Maurice C-K., P. Vamsy · InTech eBooks · 2011
Cited by 3Open access
Harry Veendrick · 2008
Cited by 0
Jeff Jessing · The electrical engineering handbook/Electrical engineering handbook series/Electrical engineering handbook · 2006
Cited by 0
Cintia Man · TSpace · 2007
Two biosensor chips, realized in standard 0.18μm CMOS, are presented with test results using biological analytes. The electrochemical biosensor, consisting of a 3×3 array of three-electrode sensing elements, occupies 1.4mm2, and can be reconfigured dynamically, via on-chip register, to perform: impedance spectroscopy, amperometric and potentiometric analysis. The design follows concepts previously published, but uses new transistor sizing and placement. Impedance spectroscopy test results are presented for the protein linker BSA; previous work is extended by presenting test results for different size on-chip aluminum-alloy electrodes offering an effective approach to detect different concentrations. The second design, the SEPTIC Detector, detects ions that flood out from a targeted bacterial cell wall when specific bacteriophages are applied. The 1.1mm2 chip is the first to confirm the efficacy of CMOS and aluminum alloy electrodes spaced to create a 0.46μm×10μm×0.9μm trench. Test results confirm identification of E. coli W3110 bacteria cells using bacteriophage λ, within 160sec.
Cited by 0Open access