A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

Garcia, R., Algredo‐Badillo, I., Morales‐Sandoval, M., Feregrino-Uribe, C., & Cumplido, R. (2013). A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Computers & Electrical Engineering, 40(1), 194–202. https://doi.org/10.1016/j.compeleceng.2013.11.014

Garcia, R., et al. “A compact FPGA-based processor for the Secure Hash Algorithm SHA-256.” Computers & Electrical Engineering, vol. 40, no. 1, 2013, pp. 194–202, https://doi.org/10.1016/j.compeleceng.2013.11.014.

Garcia, R., Ignacio Algredo‐Badillo, Miguel Morales‐Sandoval, Claudia Feregrino-Uribe, and René Cumplido. 2013. “A compact FPGA-based processor for the Secure Hash Algorithm SHA-256.” Computers & Electrical Engineering 40 (1): 194–202. https://doi.org/10.1016/j.compeleceng.2013.11.014.

Garcia, R. et al. (2013) ‘A compact FPGA-based processor for the Secure Hash Algorithm SHA-256’, Computers & Electrical Engineering, 40(1), pp. 194–202. Available at: https://doi.org/10.1016/j.compeleceng.2013.11.014.

@article{garcia2013compact,
  title = {{A compact FPGA-based processor for the Secure Hash Algorithm SHA-256}},
  author = {Garcia, R. and Algredo‐Badillo, Ignacio and Morales‐Sandoval, Miguel and Feregrino-Uribe, Claudia and Cumplido, René},
  journal = {Computers & Electrical Engineering},
  volume = {40},
  number = {1},
  pages = {194--202},
  year = {2013},
  doi = {10.1016/j.compeleceng.2013.11.014}
}