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article · Journal of the Chinese Institute of Engineers · 1990

An implementation of high‐speed decoder for double‐error‐correcting binary BCH codes in programmable logic array chip

Shyue‐Win Wei, Che‐Ho Wei, Liusheng Wang

Cited by 0Abstract and details only

Abstract

A new type of decoder for double‐error‐correcting binary BCH codes is presented. The simple and regular control clock signals of the decoder can be directly extracted from the line signals. The decoder needs only n clock cycles to decode one received word, where n is the block length of the code. A (31, 21, 5) BCH decoder is used as a hardware implementation example to illustrate the operation principle. The decoder can work at a data rate of up to 3.4Mbits/sec when it is implemented in a programmable Logic Cell Array (LCA) chip.

Cite this paper

APA 7

Wei, S., Wei, C., & Wang, L. (1990). An implementation of high‐speed decoder for double‐error‐correcting binary BCH codes in programmable logic array chip. Journal of the Chinese Institute of Engineers, 13(6), 665–672. https://doi.org/10.1080/02533839.1990.9677298

MLA 9

Wei, Shyue‐Win, et al. “An implementation of high‐speed decoder for double‐error‐correcting binary BCH codes in programmable logic array chip.” Journal of the Chinese Institute of Engineers, vol. 13, no. 6, 1990, pp. 665–72, https://doi.org/10.1080/02533839.1990.9677298.

Chicago

Wei, Shyue‐Win, Che‐Ho Wei, and Liusheng Wang. 1990. “An implementation of high‐speed decoder for double‐error‐correcting binary BCH codes in programmable logic array chip.” Journal of the Chinese Institute of Engineers 13 (6): 665–72. https://doi.org/10.1080/02533839.1990.9677298.

Harvard

Wei, S., Wei, C. and Wang, L. (1990) ‘An implementation of high‐speed decoder for double‐error‐correcting binary BCH codes in programmable logic array chip’, Journal of the Chinese Institute of Engineers, 13(6), pp. 665–672. Available at: https://doi.org/10.1080/02533839.1990.9677298.

BibTeX
@article{wei1990implementation,
  title = {{An implementation of high‐speed decoder for double‐error‐correcting binary BCH codes in programmable logic array chip}},
  author = {Wei, Shyue‐Win and Wei, Che‐Ho and Wang, Liusheng},
  journal = {Journal of the Chinese Institute of Engineers},
  volume = {13},
  number = {6},
  pages = {665--672},
  year = {1990},
  doi = {10.1080/02533839.1990.9677298}
}

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