article · IEEE Transactions on Circuits and Systems for Video Technology · 1993
A high-speed real-time binary BCH decoder
Cited by 20Abstract and details only
Abstract
A high-speed real-time decoder for t-error-correcting binary BCH codes based on a modified step-by-step decoding algorithm is presented. The average operation cycle, for decoding each received word is just equal to the block length of the codeword. The decoder is constructed of three modules: the syndrome module, the comparison module, and the error corrector. Since all of the modules can be implemented by systolic circuits, the data rate of this decoder can theoretically be up to the rate of the inverse of two logic-gate delays operating from approximately several hundreds of megabits per second to the order of gigabits per second. Thus, the decoder can be applied in broadband service and video processing. By avoiding inverse operations in the step-by-step decoding method, the circuit complexity of the decoder can be made much less than that of the standard algebraic method. The detailed circuit diagrams of the comparison module and error corrector for double- and triple-error-correcting binary BCH codes are given for illustration.>
Cite this paper
Wei, S., & Wei, C.-H. (1993). A high-speed real-time binary BCH decoder. IEEE Transactions on Circuits and Systems for Video Technology, 3(2), 138–147. https://doi.org/10.1109/76.212719
Wei, Shyue‐Win, and C.-H. Wei. “A high-speed real-time binary BCH decoder.” IEEE Transactions on Circuits and Systems for Video Technology, vol. 3, no. 2, 1993, pp. 138–47, https://doi.org/10.1109/76.212719.
Wei, Shyue‐Win, and C.-H. Wei. 1993. “A high-speed real-time binary BCH decoder.” IEEE Transactions on Circuits and Systems for Video Technology 3 (2): 138–47. https://doi.org/10.1109/76.212719.
Wei, S. and Wei, C.-H. (1993) ‘A high-speed real-time binary BCH decoder’, IEEE Transactions on Circuits and Systems for Video Technology, 3(2), pp. 138–147. Available at: https://doi.org/10.1109/76.212719.
@article{wei1993high,
title = {{A high-speed real-time binary BCH decoder}},
author = {Wei, Shyue‐Win and Wei, C.-H.},
journal = {IEEE Transactions on Circuits and Systems for Video Technology},
volume = {3},
number = {2},
pages = {138--147},
year = {1993},
doi = {10.1109/76.212719}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.
Related papers
High-speed hardware decoder for double-error-correcting binary BCH codes
Shyue‐Win Wei, Che‐Ho Wei · IEE Proceedings I Communications Speech and Vision · 1989
Cited by 27
300 megabit/second Berlekamp decoder for binary BCH codes
C. Kraft · Globecom · 2002
Cited by 1
An implementation of high‐speed decoder for double‐error‐correcting binary BCH codes in programmable logic array chip
Shyue‐Win Wei, Che‐Ho Wei, Liusheng Wang · Journal of the Chinese Institute of Engineers · 1990
Cited by 0
A Low-Complexity Step-by-Step Decoding Algorithm for Binary BCH Codes
C.-L. CHR · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2005
Cited by 8
Fast parallel decoding of double-error-correcting binary BCH codes
Thomas Aaron Gulliver, Wen Ching Lin, F. Dehne · Applied Mathematics Letters · 1998
Cited by 2Open access
A New High-speed Decoder for Double-error-correcting BCH Codes
Luo Weiyi · Jisuanji gongcheng · 2004
Cited by 0
On high-speed decoding of the (23,12,7) Golay code
Shyue‐Win Wei, Che‐Ho Wei · IEEE Transactions on Information Theory · 1990
Cited by 20
High-Speed Parallel BCH Decoder Circuit in VLSI
Dunshan Yu · Beijing Daxue Xuebao. Zirankexueban · 2008
Cited by 1