article · Defense Technical Information Center (DTIC) · 1985

A Parallel Stack Processor to Reduce Procedure-Call Overhead

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Abstract

A processor organization is presented to reduce the large overhead of procedure calls in high-level languages. In the Parallel Stack Processor, processor registers are each at the top of a hardware stack of registers. Saving processor registers on procedure call takes place in one cycle by pushing all registers simultaneously. A detailed performance model, driven by dynamic high-level language statistics, is presented. Results from the model indicate the effect on performance of the parallel stack computer architecture when compared to a processor without parallel stacks. The processor architecture is specified in the report along with a discussion of implementation details for the VLSI single-chip processor. Keywords: Parallel processors; Stacking; and Reduced Instruction Set Computer. (Author)

Cite this paper

APA 7

Eickemeyer, R. J. (1985). A Parallel Stack Processor to Reduce Procedure-Call Overhead. Defense Technical Information Center (DTIC).

MLA 9

Eickemeyer, Richard J. “A Parallel Stack Processor to Reduce Procedure-Call Overhead.” Defense Technical Information Center (DTIC), 1985.

Chicago

Eickemeyer, Richard J. 1985. “A Parallel Stack Processor to Reduce Procedure-Call Overhead.” Defense Technical Information Center (DTIC).

Harvard

Eickemeyer, R.J. (1985) ‘A Parallel Stack Processor to Reduce Procedure-Call Overhead’, Defense Technical Information Center (DTIC).

BibTeX

@article{eickemeyer1985parallel,
  title = {{A Parallel Stack Processor to Reduce Procedure-Call Overhead}},
  author = {Eickemeyer, Richard J.},
  journal = {Defense Technical Information Center (DTIC)},
  year = {1985}
}

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