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About 9,143 papers for “Microarchitecture”

Router Microarchitecture

Natalie Enright Jerger, Tushar Krishna, Li-Shiuan Peh · Synthesis lectures on computer architecture · 2017

Cited by 0

Microarchitecture level

Hitoshi Oi · 2011

Operating system machine level Partial interpretation (operating system) Level 2 Instruction set architecture level Interpretation (microprogram) or direct execution

Cited by 0

Processor Microarchitecture

Antonio González, Fernando Latorre, Grigorios Magklis · Synthesis lectures on computer architecture · 2011

Cited by 5

Processor Microarchitecture

Michel Dubois, Murali Annavaram, Per Stenström · 2025

Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. Self-contained yet concise, the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. This edition has a more streamlined structure, with the reliability and other technology background sections now included in the appendix. New material includes a chapter on GPUs, providing a comprehensive overview of their microarchitectures; sections focusing on new memory technologies and memory interfaces, which are key to unlocking the potential of parallel computing systems; deeper coverage of memory hierarchies including DRAM architectures, compression in memory hierarchies and an up-to-date coverage of prefetching. Practical examples demonstrate concrete applications of definitions, while the simple models and codes used throughout ensure the material is accessible to a broad range of computer engineering/science students.

Cited by 0

Achievement in Microarchitecture

Leah Hoffmann · Communications of the ACM · 2023

David Papworth, a 30-year veteran of Intel, on what led to the P6 microprocessor and how that changed the microarchitectural paradigm.

Cited by 1Open access

The ARM11 microarchitecture

David Cormie · 2002

The ARM11 ™ microarchitecture is the first implementation of the ARMv6 instruction set architecture, and forms the basis of a new family of ARM11 cores. The microarchitecture is the detailed definition of the internal design, and hardware resources, which supports the ARMv6 architectural specification. The key objective in developing the ARM11 microarchitecture was to deliver high performance at low power and low cost. This paper examines the specific features of the new microarchitecture, and explains why the design meets the needs of next-generation wireless and portable consumer products. ARMv6 Architecture The first step in the implementation of a new generation of microprocessors is the definition of the architecture. The architecture describes the rules for how the microprocessor will behave, but without constraining or specifying how it will be built. The definition of the architecture provides the specification for the interface with the outside world – enabling operating system, application and development support to be planned and implemented. In detailed terms, the microprocessor architecture defines the processor’s instruction set, the programmer’s model, and how the processor interfaces with its closest memory resources. The latest ARM ® architecture – ARMv6, was announced in October 2001. ARMv6 builds on many of the successful architecture specifications developed by ARM over the last 10 years. Successive ARM architectures have provided the foundation for ARM’s market leadership in 16- and 32-bit microprocessor cores.

Cited by 0

Post-Fabrication Microarchitecture

Chanchal Kumar, Anirudh Seshadri, Aayush Chaudhary et al. · 2021

Microarchitectural enhancements that improve performance generally, across many workloads, are favored in superscalar processor design. Targeting general performance is necessary but it also constrains some microarchitecture innovation. We explore relieving this constraint, via a new paradigm called Post-Fabrication Microarchitecture (PFM). A high-performance superscalar core is coupled with a reconfigurable logic fabric, RF. A programmable interface, or Agent, allows for RF to observe and microarchitecturally intervene at key pipeline stages of the superscalar core. New microarchitectural components, specific to applications, are synthesized on-demand to RF. All instructions still flow through the superscalar pipeline, as usual, but their execution is streamlined (better instructions per cycle (IPC)) through microarchitectural intervention by RF. Our research shows that one can achieve large speedups of individual applications, by analyzing their bottlenecks and providing customized microarchitectural solutions to target these bottlenecks. Examples of PFM use-cases explored in this paper include custom branch predictors and data prefetchers.

Cited by 4

Data threaded microarchitecture

Dick Wilmot · ACM SIGARCH Computer Architecture News · 1998

article Free Access Share on Data threaded microarchitecture Author: Dick Wilmot View Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 26Issue 5Dec. 1998 pp 22–32https://doi.org/10.1145/306240.306248Online:01 December 1998Publication History 0citation16DownloadsMetricsTotal Citations0Total Downloads16Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Cited by 0Open access

Temperature-aware microarchitecture

Kevin Skadron, Mircea R. Stan, Wei Huang et al. · ACM SIGARCH Computer Architecture News · 2003

With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package's capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies.This paper describes HotSpot, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finite-element simulation. The paper also introduces several effective methods for dynamic thermal management (DTM): "temperature-tracking" frequency scaling, localized toggling, and migrating computation to spare hardware units. Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM.

Cited by 317

Microarchitecture level Hardware

Hitoshi Oi · 2010

Operating system machine level Partial interpretation (operating system) Level 2 Instruction set architecture level Interpretation (microprogram) or direct execution

Cited by 0

Temperature-aware microarchitecture

Kevin Skadron, Mircea R. Stan, Wei Huang et al. · 2003

With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package's capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies.This paper describes HotSpot, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finite-element simulation. The paper also introduces several effective methods for dynamic thermal management (DTM): "temperature-tracking" frequency scaling, localized toggling, and migrating computation to spare hardware units. Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM.

Cited by 1,131

Microarchitecture-Independent Snapshots

Kenneth C. Barr, Krste Asanović, Kenneth C. Barr · 2006

Computer architects rely heavily on software simulation to evaluate, refine, and validate new designs before they are implemented. However, simulation time continues to increase as computers become more complex and multicore designs become more common. This thesis investigates software structures and algorithms for quickly simulating modern cache-coherent multiprocessors by amortizing the time spent to simulate the memory system and branch predictors. The Memory Timestamp Record (MTR) summarizes the directory and cache state of a multiprocessor system in a compact data structure. A single MTR snapshot is versatile enough to reconstruct the microarchitectural state resulting from various coherence protocols and cache organizations. The MTR may be quickly updated by each simulated processor during a fast-forwarding phase and optionally stored off-line for reuse. To fill large branch prediction tables, we introduce Branch Predictor-based Compression (BPC) which compactly stores a branch trace so that it may be used to fill in any branch predictor structure. An entire BPC trace requires less space than single discrete predictor

Cited by 0