article · 2019

Netlist Optimization by Gate Merging

Cited by 3Abstract and details only

Abstract

The small number of logic functions in a traditional cell library limits the optimization of digital design regarding transistors, wires, and vias count. It affects traditional quality metrics, like area and total wire length. Our new library free approach enables such optimization by using tools for automatic layout synthesis of any transistor network. Using the traditional cell-based design flow to generate the initial netlist, we postprocess it considering to replace groups of cells by a single new cell of equivalent logic, which is not available in the cell library. Tests were performed over a standard benchmark, using a predictive 45nm cell library. Our approach reduces on average the number of transistors of a circuit by 21% when compared to a traditional solution. When to other logic minimization tools, it reduces transistor count by 2%, and by consequence, we obtain an average reduction of 9% on the number of wire segments, 5% in total wire length and 6% fewer pins. It also impacts the traditional performance metrics, demanding in 5% less area.

Cite this paper

APA 7

Conceição, C., & Reis, R. (2019). Netlist Optimization by Gate Merging. https://doi.org/10.1109/vlsi-soc.2019.8920291

MLA 9

Conceição, Calebe, and Ricardo Reis. “Netlist Optimization by Gate Merging.” 2019, pp. 236–37, https://doi.org/10.1109/vlsi-soc.2019.8920291.

Chicago

Conceição, Calebe, and Ricardo Reis. 2019. “Netlist Optimization by Gate Merging.” https://doi.org/10.1109/vlsi-soc.2019.8920291.

Harvard

Conceição, C. and Reis, R. (2019) ‘Netlist Optimization by Gate Merging’. Available at: https://doi.org/10.1109/vlsi-soc.2019.8920291.

BibTeX

@article{conceicao2019netlist,
  title = {{Netlist Optimization by Gate Merging}},
  author = {Conceição, Calebe and Reis, Ricardo},
  pages = {236--237},
  year = {2019},
  doi = {10.1109/vlsi-soc.2019.8920291}
}

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