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About 2,033 papers for “Netlist”

Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison

Reilly McKendrick, Keenan Faulkner, Jeffrey Goeders · 2023

Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation information to perform a series of transformations on the netlist, which do not affect its functionality, but ensure it structurally matches what is physically implemented on the FPGA. Second, we present a structural mapping and equivalence checking algorithm that verifies this physical netlist exactly matches the bitstream. We validate this process on several benchmark designs, including checking for false positives by injecting hundreds of design modifications.

Cited by 4

Adaptive methods for netlist partitioning

Buntine, Lixin Su, Newton et al. · 1997

An algorithm that remains in use at the core of many partitioning systems is the Kemighan-Lin algorithm and a variant the Fidducia-Matheysses (FM) algorithm. To understand the FM algorithm we applied principles of data engineering where visualization and statistical analysis are used to analyze the run-time behavior. We identified two improvements to the algorithm which, without clustering or an improved heuristic function, bring the performance of the algorithm near that of more sophisticated algorithms. One improvement is based on the observation, explored empirically, that the full passes in the FM algorithm appear comparable to a stochastic local restart in the search. We motivate this observation with a discussion of recent improvements in Monte Carlo Markov Chain methods in statistics. The other improvement is based on the observation that when an FM-like algorithm is run 20 times and the best run chosen, the performance trace of the algorithm on earlier runs is useful data for learning when to abort a later run. These improvements, implemented with a simple adaptive scheme, are orthogonal to techniques used in state-of-the-art implementations, and therefore should be applicable to other VLSI optimization algorithms.

Cited by 3

Netlist Optimization by Gate Merging

Calebe Conceição, Ricardo Reis · 2019

The small number of logic functions in a traditional cell library limits the optimization of digital design regarding transistors, wires, and vias count. It affects traditional quality metrics, like area and total wire length. Our new library free approach enables such optimization by using tools for automatic layout synthesis of any transistor network. Using the traditional cell-based design flow to generate the initial netlist, we postprocess it considering to replace groups of cells by a single new cell of equivalent logic, which is not available in the cell library. Tests were performed over a standard benchmark, using a predictive 45nm cell library. Our approach reduces on average the number of transistors of a circuit by 21% when compared to a traditional solution. When to other logic minimization tools, it reduces transistor count by 2%, and by consequence, we obtain an average reduction of 9% on the number of wire segments, 5% in total wire length and 6% fewer pins. It also impacts the traditional performance metrics, demanding in 5% less area.

Cited by 3

HCNC: High Capacity Netlist Compare

Rahul Razdan · 2002

The author describes HCNC (High Capacity Netlist Compare), a technique for netlist comparison that uses the natural hierarchy of the transistor circuit to significantly increase the capacity of traditional netlist comparison algorithms. Since the natural hierarchy of the circuit is used, HCNC does not require hierarchical information from the user. HCNC also has some desirable properties for error recovery. Results from the network comparison of several large industrial circuits shall show the viability of this algorithm.

Cited by 1

Hardware Protection and Authentication Through Netlist

Rajat Subhra Chakraborty, Swarup Bhunia · 2008

Abstract—Hardware Intellectual Property (IP) cores have emerged as an integral part of modern System–on–Chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs and to prevent revenue loss due to IP piracy. In this paper, we propose a novel design methodology for hardware IP protection and authentication using netlist level authentication. The proposed methodology can be integrated in the SoC design and manufacturing flow to provide hardware protection to the IP vendors, the chip designer, and the system designer. Simulation results on ISCAS–89 benchmark circuits show that we can achieve high levels of security through a well– formulated obfuscation scheme at less than 10 % area overhead under delay constraint. Index Terms — Design for security, IP piracy, hardware authentication, hardware obfuscation, hardware protection. I.

Cited by 0

Netlist-Aware Mixed-Cell-Height Legalization

Ting Liang, Weijie Chen, Bin Liao · Electronics · 2025

Mixed cell heights pose significant challenges to placement in large-scale integrated circuits. In particular, the heterogeneity of cells remarkably complicates the legalization of mixed-cell-height cells. To preserve the global placement results as much as possible, we propose to directly optimize the total displacement through l1-norm minimization. For illegal cells that extend beyond the chip boundaries, the netlist information of cells is taken into account and a mixed-integer programming model is employed to determine the optimal placement that minimizes the half-perimeter wirelength (HPWL) variation. This joint optimization strikes a balance between minimizing geometric displacement and HPWL, ensuring that the legalization process remains compact to achieve better placement performance. Experimental evaluations on mixed-cell-height benchmarks demonstrate that the proposed approach achieves smaller total displacement and notably lower HPWL variation within practical time limits compared with state-of-the-art legalization methods. Moreover, this work provides a scalable foundation for future extensions to three-dimensional (3D) IC placement legalization.

Cited by 0Open access

Koios benchmarks' netlist files (BLIF format)

Aman Arora, Andrew Boutros, Seyed Alireza Damghani et al. · Zenodo (CERN European Organization for Nuclear Research) · 2022

Koios is a benchmark suite for FPGA architecture and CAD exploration. It contains circuits from the Deep Learning domain. Here we are uploading the netlist files for these designs obtained by synthesizing the Verilog designs using Intel Quartus for Intel Stratix IV architecture. For more details see: https://docs.verilogtorouting.org/en/latest/vtr/benchmarks/#koios-benchmarks https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow/benchmarks/verilog/koios

Cited by 0Open access

AMSNet: Netlist Dataset for AMS Circuits

Zhuofu Tao, Yichen Shi, Yiru Huo et al. · 2024

Today’s analog/mixed-signal (AMS) integrated circuit (IC) designs demand substantial manual intervention. The advent of multimodal large language models (MLLMs) has unveiled significant potential across various fields, suggesting their applicability in streamlining large-scale AMS IC design as well. A bottleneck in employing MLLMs for automatic AMS circuit generation is the absence of a comprehensive dataset delineating the schematic-netlist relationship. We therefore design an automatic technique for converting schematics into netlists, and create dataset AMSNet, encompassing transistor-level schematics and corresponding SPICE format netlists. With a growing size, AMSNet can significantly facilitate exploration of MLLM applications in AMS circuit design. We have made the current version of database and associated generation tool public, both of which are expanded quickly.

Cited by 13

Multi-target AHPL netlist format translator

Teng-I Wang · UA Campus Repository (The University of Arizona) · 1995

AENT91 and AENT-TTL are AHPL to EDIF netlist translator for the AHPL hardware programming language. Although they are able to provide connections to L-EditTM, GateSimTM and OrCAD/VSTTM some embedded limitations inhibit them from providing more useful connections to other advanced commercial CAD tools. This thesis describes a new AHPL Netlist Format Translator (ANFT) which serves as a multi-target translator with some local optimization processes for AHPL. The limitations of AENT91 and AENT-TTL as well as the design considerations of ANFT are discussed in the first of the three parts of this thesis. Implementation details are provided in the second part. In the last part, tests of ANFT output files and comparisons of results from AENT91, AENT-TTL and ANFT translated AHPL benchmarks are presented. The results show that ANFT not only provides better results but also successfully connects AHPL to more commercial CAD tool systems.

Cited by 0

From the bitstream to the netlist

Jean-Baptiste Note, Éric Rannaud · 2008

This poster presents an in-depth analysis of the Xilinx bitstream file format. This theoretical analysis is backed by a simple and efficient implementation of a reverse-engineering tool for Xilinx bitstreams. The development process followed these lines. First, publicly available documentation from Xilinx has been analyzed; then some custom assumptions about the bitstream format have been made. This information allowed a suitable algorithm to be run on well-chosen bitstreams. The output from this automated analysis step is a database which relates raw bitstream data to low-level netlist elements. This database is subsequently used as input to an efficient bitstream compiler which can either generate a bitstream from a low-level (XDL) description of the netlist, or conversely decompile any given bitstream to its low-level netlist elements. This work has been validated for the spartan3, virtex2, virtex4 and virtex5 FPGA lines from Xilinx. Decompiling a bitstream is very fast; it is two orders of magnitude faster than the reverse operation of compilation with Xilinx' bitgen. This work aims to raise awareness about security issues for users of FPGAs. It also makes custom compilation and low-level tinkering with bitstreams - a la JBits - possible

Cited by 158

Functionality matters in netlist representation learning

Ziyi Wang, Chen Bai, Zhuolun He et al. · Proceedings of the 59th ACM/IEEE Design Automation Conference · 2022

Learning feasible representation from raw gate-level netlists is essential for incorporating machine learning techniques in logic synthesis, physical design, or verification. Existing message-passing-based graph learning methodologies focus merely on graph topology while overlooking gate functionality, which often fails to capture underlying semantic, thus limiting their generalizability. To address the concern, we propose a novel netlist representation learning framework that utilizes a contrastive scheme to acquire generic functional knowledge from netlists effectively. We also propose a customized graph neural network (GNN) architecture that learns a set of independent aggregators to better cooperate with the above framework. Comprehensive experiments on multiple complex real-world designs demonstrate that our proposed solution significantly outperforms state-of-the-art netlist feature learning flows.

Cited by 44