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conference paper · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 2005

An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts

H. Dwyer, H. C. Torng

Cited by 9Abstract and details only

Abstract

The achievement of fast, precise interrupts and the implementation of multiple levels of branch predictions are two of the problems associated with the dynamic scheduling of instructions for superscalar processors. Their solution is especially difficult if short cycle time operation is desired. We present solutions to these problems through the development of the Fast Dispatch Stack (FDS) system. We show that the FDS is capable of scheduling storage, branch, and register-toregister instructions for concurrent and out-oforder executions; the FDS implements fast and precise interrupts in a natural, efficient way; and it facilitates speculative execution -- Instructions preceding and following one or more predicted conditional branch instructions may issue. When necessary, their effects are undone in one machine cycle. We evaluated the FDS system with extensive simulations.

Cite this paper

APA 7

Dwyer, H., & Torng, H. C. (2005). An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts. IEEE/ACM International Symposium on Microarchitecture (MICRO), 272–281. https://doi.org/10.1109/micro.1992.697031

MLA 9

Dwyer, H., and H. C. Torng. “An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts.” IEEE/ACM International Symposium on Microarchitecture (MICRO), 2005, pp. 272–81, https://doi.org/10.1109/micro.1992.697031.

Chicago

Dwyer, H., and H. C. Torng. 2005. “An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts.” IEEE/ACM International Symposium on Microarchitecture (MICRO): 272–81. https://doi.org/10.1109/micro.1992.697031.

Harvard

Dwyer, H. and Torng, H.C. (2005) ‘An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts’, IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 272–281. Available at: https://doi.org/10.1109/micro.1992.697031.

BibTeX
@article{dwyer2005order,
  title = {{An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts}},
  author = {Dwyer, H. and Torng, H. C.},
  journal = {IEEE/ACM International Symposium on Microarchitecture (MICRO)},
  pages = {272--281},
  year = {2005},
  doi = {10.1109/micro.1992.697031}
}

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