Adding Fast Interrupts to Superscalar Processors

Abstract

The hardware cost of taking an interrupt is increasing as processors become more superscalar. Using FLIP, an aggressively superscalar processor which we have designed and tested in Verilog, we demonstrate that interrupts can be fast and inexpensive. We trace individual signals through FLIP's pipeline stages to show that fast interrupts require negligible new hardware. Except for linkage information, interrupts reuse existing branch mechanisms. An asynchronous interrupt acts as an immediate jump instruction, while a synchronous interrupt acts as a mispredicted branch. Although we concentrate on user-level interrupts, we show that kernel-level interrupts can be handled identically with the addition of protection mode bits to identify the protection mode of every outstanding instruction. In blending fast interrupts into the superscalar processor, we address two new problems. The first problem arises from fast synchronous interrupts. Because most instructions can cause an interrupt, the pr...

Cite this paper

@article{henry2005adding,
  title = {{Adding Fast Interrupts to Superscalar Processors}},
  author = {Henry, Dana S.},
  year = {2005}
}

Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.

Related papers