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article · 1984

A 1K-gate GaAs gate array

Y. Ikawa, Nagaoki Toyoda, M. Mochisuki, Tomoki P. Terada, K. Kanazawa, M. Hirose, T. Mizoguchi, A. Hojo

Cited by 7Abstract and details only

Abstract

A 1050-gate GaAs gate array connected as a 6 × 6b parallel multiplier, which exhibits a multiplication time of 10.6ns and 350mW power dissipation, will be covered.

Cite this paper

APA 7

Ikawa, Y., Toyoda, N., Mochisuki, M., Terada, T. P., Kanazawa, K., Hirose, M., Mizoguchi, T., & Hojo, A. (1984). A 1K-gate GaAs gate array. https://doi.org/10.1109/isscc.1984.1156640

MLA 9

Ikawa, Y., et al. “A 1K-gate GaAs gate array.” 1984, pp. 40–41, https://doi.org/10.1109/isscc.1984.1156640.

Chicago

Ikawa, Y., Nagaoki Toyoda, M. Mochisuki, Tomoki P. Terada, K. Kanazawa, M. Hirose, T. Mizoguchi, and A. Hojo. 1984. “A 1K-gate GaAs gate array.” https://doi.org/10.1109/isscc.1984.1156640.

Harvard

Ikawa, Y. et al. (1984) ‘A 1K-gate GaAs gate array’. Available at: https://doi.org/10.1109/isscc.1984.1156640.

BibTeX
@article{ikawa1984gate,
  title = {{A 1K-gate GaAs gate array}},
  author = {Ikawa, Y. and Toyoda, Nagaoki and Mochisuki, M. and Terada, Tomoki P. and Kanazawa, K. and Hirose, M. and Mizoguchi, T. and Hojo, A.},
  pages = {40--41},
  year = {1984},
  doi = {10.1109/isscc.1984.1156640}
}

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A 6,000-gate CMOS gate array

T. Itoh, M. Takechi, M. Fujita et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 1982

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