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article · 2002

A flexible gate array for high speed and high density applications

J. Gallia, R J Landers, Ching-Hao Shaw, T.G.W. Blake, W. Banzhaf

Cited by 0Abstract and details only

Abstract

A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm/sup 2/ routed density in a 0.5 /spl mu/m TLM CMOS gate array. Compared to previous 5 V 0.7 /spl mu/m gate arrays, the new basecell provides a 2.5/spl times/ density improvement, 30% speed-up, and 70% lower power. NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAMs feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions.

Cite this paper

APA 7

Gallia, J., Landers, R. J., Shaw, C.-H., Blake, T., & Banzhaf, W. (2002). A flexible gate array for high speed and high density applications. https://doi.org/10.1109/cicc.1995.518125

MLA 9

Gallia, J., et al. “A flexible gate array for high speed and high density applications.” 2002, pp. 1–4, https://doi.org/10.1109/cicc.1995.518125.

Chicago

Gallia, J., R J Landers, Ching-Hao Shaw, T.G.W. Blake, and W. Banzhaf. 2002. “A flexible gate array for high speed and high density applications.” https://doi.org/10.1109/cicc.1995.518125.

Harvard

Gallia, J. et al. (2002) ‘A flexible gate array for high speed and high density applications’. Available at: https://doi.org/10.1109/cicc.1995.518125.

BibTeX
@article{gallia2002flexible,
  title = {{A flexible gate array for high speed and high density applications}},
  author = {Gallia, J. and Landers, R J and Shaw, Ching-Hao and Blake, T.G.W. and Banzhaf, W.},
  pages = {1--4},
  year = {2002},
  doi = {10.1109/cicc.1995.518125}
}

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