article · Electronics Letters · 1986

Overlaid CMOS

S.D.S. Malhi, K.E. Bean, R. Sunderesan, L.R. Hite

Cited by 1Abstract and details only

Abstract

A CMOS structure where the source and drain terminals of the MOSFETs are in polysilicon overlaid on top of a thick oxide and the channel is in single-crystal silicon is described, utilising a 970°C SiH4 CVD process which simultaneously deposits epitaxial silicon on the exposed silicon substrate and polysilicon on oxide. The structure allows a more compact CMOS inverter layout and reduced source/drain parasitic capacitances.

Cite this paper

APA 7

Malhi, S., Bean, K., Sunderesan, R., & Hite, L. (1986). Overlaid CMOS. Electronics Letters, 22(11), 598–599. https://doi.org/10.1049/el:19860406

MLA 9

Malhi, S.D.S., et al. “Overlaid CMOS.” Electronics Letters, vol. 22, no. 11, 1986, pp. 598–99, https://doi.org/10.1049/el:19860406.

Chicago

Malhi, S.D.S., K.E. Bean, R. Sunderesan, and L.R. Hite. 1986. “Overlaid CMOS.” Electronics Letters 22 (11): 598–99. https://doi.org/10.1049/el:19860406.

Harvard

Malhi, S. et al. (1986) ‘Overlaid CMOS’, Electronics Letters, 22(11), pp. 598–599. Available at: https://doi.org/10.1049/el:19860406.

BibTeX

@article{malhi1986overlaid,
  title = {{Overlaid CMOS}},
  author = {Malhi, S.D.S. and Bean, K.E. and Sunderesan, R. and Hite, L.R.},
  journal = {Electronics Letters},
  volume = {22},
  number = {11},
  pages = {598--599},
  year = {1986},
  doi = {10.1049/el:19860406}
}

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