article · Èlektronnoe modelirovanie · 2023

Hardware Decompressor Design

Cited by 1Abstract and details only

Abstract

The common lossless compression algorithms were analyzed, and the LZW algorithm was selected for the hardware implementation. To express parallelism, this algorithm is represented as a cyclo-dynamic dataflow (CDDF). A hardware synthesis method for designing pipelined datapath is proposed, which optimizes CDDF considering the features of the FPGA primitives and maps it to hardware using VHDL language description. Using this method, an LZW de¬compressor is developed, which exhibits a high performance-to-hardware cost ratio. The de¬com¬¬¬pressor can be utilized in communication channels and other application-specific systems for data loading from memory, generating graphical stencils, and more.

Cite this paper

APA 7

Sergiyenko, A., & Mozghovyi, I. (2023). Hardware Decompressor Design. Èlektronnoe modelirovanie, 45(5), 113–128. https://doi.org/10.15407/emodel.45.05.113

MLA 9

Sergiyenko, Anatoliy, and Ivan Mozghovyi. “Hardware Decompressor Design.” Èlektronnoe modelirovanie, vol. 45, no. 5, 2023, pp. 113–28, https://doi.org/10.15407/emodel.45.05.113.

Chicago

Sergiyenko, Anatoliy, and Ivan Mozghovyi. 2023. “Hardware Decompressor Design.” Èlektronnoe modelirovanie 45 (5): 113–28. https://doi.org/10.15407/emodel.45.05.113.

Harvard

Sergiyenko, A. and Mozghovyi, I. (2023) ‘Hardware Decompressor Design’, Èlektronnoe modelirovanie, 45(5), pp. 113–128. Available at: https://doi.org/10.15407/emodel.45.05.113.

BibTeX

@article{sergiyenko2023hardware,
  title = {{Hardware Decompressor Design}},
  author = {Sergiyenko, Anatoliy and Mozghovyi, Ivan},
  journal = {Èlektronnoe modelirovanie},
  volume = {45},
  number = {5},
  pages = {113--128},
  year = {2023},
  doi = {10.15407/emodel.45.05.113}
}

Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.