article · 2007
Cost and Performance Analysis of Scalable Parallel Architectures
Sotirios G. Ziavras
Cited by 0Abstract and details only
Abstract
Interprocessor connection networks with very good topological properties are often impossible to build because of their prohibitively high wire complexity. Such a network is the generalized hypercube (GH) that supports full-connectivity of all its nodes in each dimension. We present here the class of HOW interprocessor connections which are capable of lower complexity than GHs, comparable performance, and better scalability. We analyze the hardware cost of HOWs, present communications algorithms for 2-D HOWs, and carry out performance comparisons with binary hypercubes and GHs. Keywords: Parallel computer, interconnection network, cost analysis, communications operations. 1 Introduction Developing low-complexity, high-bisection bandwidth, and low-latency networks to interconnect processors (PEs) in MPP systems is a Herculean task. Several message passing interconnection networks have been proposed for parallel computers [1]. To support scalability, current approaches most often use b...
Cite this paper
Ziavras, S. G. (2007). Cost and Performance Analysis of Scalable Parallel Architectures.
Ziavras, Sotirios G. “Cost and Performance Analysis of Scalable Parallel Architectures.” 2007.
Ziavras, Sotirios G. 2007. “Cost and Performance Analysis of Scalable Parallel Architectures.”
Ziavras, S.G. (2007) ‘Cost and Performance Analysis of Scalable Parallel Architectures’.
@article{ziavras2007cost,
title = {{Cost and Performance Analysis of Scalable Parallel Architectures}},
author = {Ziavras, Sotirios G.},
year = {2007}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.