article · 2008

Power-Aware Operand Delivery

Cited by 0Abstract and details only

Abstract

Based on operand delivery, existing microprocessors can be categorized into architected register file (ARF) or physical register file (PRF) machines, both with or without payload RAM (PL). Though many previous generation microprocessors use a PRF without PL, the trend of newer microprocessors targeting lower power environments seem to be moving towards ARF with PL. We quantitatively analyze power consumption of different machine styles: ARF with PL, ARF without PL, PRF with PL, and PRF only machine. Our result shows that PRF without PL consumes the least amount of power and is fundamentally the best approach for building poweraware out-of-order microprocessors.

Cite this paper

APA 7

(2008). Power-Aware Operand Delivery.

MLA 9

“Power-Aware Operand Delivery.” 2008.

Chicago

2008. “Power-Aware Operand Delivery.”

Harvard

(2008) ‘Power-Aware Operand Delivery’.

BibTeX

@article{anon2008power,
  title = {{Power-Aware Operand Delivery}},
  year = {2008}
}

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