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About 1,900 papers for “Operand”

Operand

Encyclopedic Dictionary of Genetics, Genomics and Proteomics · 2004

Cited by 0

operand, n.

Oxford University Press eBooks · 2023

Cited by 0

Multi-operand floating-point addition utilizing operand sorting

F. Hartwig, A. Lacroix · 2003

In many signal processing applications repeated additions have to be calculated with a considerable number of operands. It is known that proper sorting of operands has a positive influence on the precision of the result of multioperand floating-point additions. This is investigated for different operand statistics and for proper sorting strategies. In addition to successive addition techniques, adder trees are included in the investigation. The densities of the addition errors for different floating-point addition methods are compared.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 4

Execution Operand fetch

Yoshihiro Iida, Naohiko Shimizu · 2014

processor, implemented it on an FPGA. We also designed ANSI C development tools an FPGA base-board which has SRAM, Serial and IDE interface, and run UNIX V6 on this system. In this paper, we describe a feature of a design of POP-11/40, base-board and UNIX V6. Condition codes operation

Cited by 0

IEEE Computer Architecture Letters Operand Registers and Explicit Operand Forwarding

James Balfour, R. Curtis Harting, William J. Dally Fellow · 2013

Abstract—Operand register files are small, inexpensive register files that are integrated with function units in the execute stage of the pipeline, effectively extending the pipeline operand registers into register files. Explicit operand forwarding lets software opportunistically orchestrate the routing of operands through the forwarding network to avoid writing ephemeral values to registers. Both mechanisms let software capture short-term reuse and locality close to the function units, improving energy efficiency by allowing a significant fraction of operands to be delivered from inexpensive registers that are integrated with the function units. An evaluation shows that capturing operand bandwidth close to the function units allows operand registers to reduce the energy consumed in the register files and forwarding network of an embedded processor by 61%, and allows explicit forwarding to reduce the energy consumed by 26%. Index Terms—energy efficient register organization, operand registers, explicit operand forwarding, embedded processor I.

Cited by 0

Exploiting Partial Operand Knowledge

Brian Mestan University, Brian R. Mestan · 2007

Conventional microprocessor designs treat register operands&amp;apos; as atomic units&amp;apos;. In such designs, no portion of an operand may be consumed until the entire operand has been produced. In practice, logic circuits&amp;apos; and arithmetic units&amp;apos; that generate some portion of an operand in advance of the remaining portions are both feasible and desirable, and have been employed in several existing designs&amp;apos;. In this report, we propose to exploit the early partial knowledge of an instructionS&amp;apos; input operands&amp;apos; for overlapping the execution of dependent instructions and resolving unknown dependences.

Cited by 0

Software-Controlled Operand-Gating

Ramon Canal, et al. · 2008

Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method for implementing software-controlled power gating is proposed and evaluated. The instruction set architecture (ISA) is enhanced to include opcodes that specify operand widths (if not already included in the ISA). A compiler or a binary translator uses statically available information to determine initial value ranges. The technique is enhanced through a profile-based analysis that results in the specialization of certain code regions for a given value range. After the analysis, instruction opcodes are assigned using the minimum required width. To evaluate this technique the Alpha instruction set is enhanced to include opcodes for 8, 16, and 32 bit operands. Applying the proposed software technique to the SpecInt95 benchmarks results in energy-delay 2 savings of 14%. When combined with previously proposed hardware-based techniques, the energy-delay 2 benefit is 28%.

Cited by 0

Multi-operand associative arithmetic

Isaac D. Scherson, S. Ruhman · 1983

Multi-operand associative techniques attain their full power in algorithms Where the data may be recast into disjoint data sets, all acted upon concurrently, each by a different operand common to the set. But the multi-operand approach can also serve to enhance arithmetic operations significantly. The speed-up of associative multiplication by handling a number of multiplier bits at a time is described and analyzed, including an effective algorithm for a limited sum of products. The most complex process treated is convolution, which serves to illustrate the enhancement of an extended sum of products. Any number of vectors stored in memory can be convolved simultaneously by a common filter vector. Execution time is 45 milliseconds for 1024 element data and filter vectors, 2048 element results, and l6-bit precision.

Cited by 0

Software-controlled operand-gating

Canal Corretger, Ramon, González Colás, Antonio María, Smith, James E. · RECERCAT (Consorci de Serveis Universitaris de Catalunya)

Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method for implementing software-controlled power gating is proposed and evaluated. The instruction set architecture (ISA) is enhanced to include opcodes that specify operand widths (if not already included in the ISA). A compiler or a binary translator uses statically available information to determine initial value ranges. The technique is enhanced through a profile-based analysis that results in the specialization of certain code regions for a given value range. After the analysis, instruction opcodes are assigned using the minimum required width. To evaluate this technique the Alpha instruction set is enhanced to include opcodes for 8, 16, and 32 bit operands. Applying the proposed software technique to the Speclnt95 benchmarks results in energy-delay savings of 14%. When combined with previously proposed hardware-based techniques, the energy-delay benefit is 28%.

Cited by 0Open access

Power-Aware Operand Delivery

2008

Based on operand delivery, existing microprocessors can be categorized into architected register file (ARF) or physical register file (PRF) machines, both with or without payload RAM (PL). Though many previous generation microprocessors use a PRF without PL, the trend of newer microprocessors targeting lower power environments seem to be moving towards ARF with PL. We quantitatively analyze power consumption of different machine styles: ARF with PL, ARF without PL, PRF with PL, and PRF only machine. Our result shows that PRF without PL consumes the least amount of power and is fundamentally the best approach for building poweraware out-of-order microprocessors.

Cited by 0

Software-controlled operand-gating

R. Canal, Antonio González, J.E. Smith · QRU Quaderns de Recerca en Urbanisme · 2004

Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method for implementing software-controlled power gating is proposed and evaluated. The instruction set architecture (ISA) is enhanced to include opcodes that specify operand widths (if not already included in the ISA). A compiler or a binary translator uses statically available information to determine initial value ranges. The technique is enhanced through a profile-based analysis that results in the specialization of certain code regions for a given value range. After the analysis, instruction opcodes are assigned using the minimum required width. To evaluate this technique the Alpha instruction set is enhanced to include opcodes for 8, 16, and 32 bit operands. Applying the proposed software technique to the Speclnt95 benchmarks results in energy-delay savings of 14%. When combined with previously proposed hardware-based techniques, the energy-delay benefit is 28%.

Cited by 12Open access

Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport

2008

As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural design focus from operation computation to operand transport. Operand bypass networks of out-oforder superscalar processors are particularly demanding of wiring resources. Forwarding path delay has become a limiting factor of processor performance. This paper proposes a novel technology-based methodology to evaluate bypass network configurations by predicting operand transport cost. It combines technology modeling techniques with cycle-accurate simulation of benchmark applications to characterize operand movement and storage requirements. Our analysis shows that the operand transport cost heavily depends on the physical location of functional units (FUs) and instruction steering strategy. We propose a traffic-based placement which places FUs based on the transport distribution pattern; and a geometry-driven instruction steering which tries to assign each pair of dependent instructions to adjacent computing resources. Performance is evaluated on an aggressive eight-way, 16 functional unit processor operating at 1.9 GHz in 100 nm technology. Combining these two techniques, the IPC penalties resulting from wire delay latency can be kept within 6.8 % of the ideal zero bypass delay processor for Spec2000Int and within 5.5 % for MediaBench. 1.

Cited by 0

Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport

Hong‐Kyu Kim, D.S. Wills, Frederick W. B. Li · 2005

As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift micro-architectural design focus from operation computation to operand transport. Operand bypass networks of out-of-order superscalar processors are particularly demanding of wiring resources. Forwarding path delay has become a limiting factor of processor performance. This paper proposes a novel technology-based methodology to evaluate bypass network configurations by predicting operand transport cost. It combines technology modeling techniques with cycle-accurate simulation of benchmark applications to characterize operand movement and storage requirements. Our analysis shows that the operand transport cost heavily depends on the physical location of functional units (FUs) and instruction steering strategy. We propose a traffic-based placement which places FUs based on the transport distribution pattern; and a geometry-driven instruction steering which tries to assign each pair of dependent instructions to adjacent computing resources. Performance is evaluated on an aggressive eight-way, 16 functional unit processor operating at 1.9 GHz in 100 nm technology. Combining these two techniques, the IPC penalties resulting from wire delay latency can be kept within 6.8% of the ideal zero bypass delay processor for Spec2000Int and within 5.5% for MediaBench.

Cited by 2