article · 2014

A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35µm CMOS Technology

Minoru Watanabe, Fuminori Kobayashi

Cited by 0Abstract and details only

Abstract

High-speed reconfigurable processors have been developed in recent years: they are DAP/DNA chips and DRP chips [1][2]. These devices can be changed from one context to another context at every clock cycle in a few nanoseconds.

Cite this paper

APA 7

Watanabe, M., & Kobayashi, F. (2014). A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35µm CMOS Technology.

MLA 9

Watanabe, Minoru, and Fuminori Kobayashi. “A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35µm CMOS Technology.” 2014.

Chicago

Watanabe, Minoru, and Fuminori Kobayashi. 2014. “A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35µm CMOS Technology.”

Harvard

Watanabe, M. and Kobayashi, F. (2014) ‘A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35µm CMOS Technology’.

BibTeX

@article{watanabe2014gate,
  title = {{A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35µm CMOS Technology}},
  author = {Watanabe, Minoru and Kobayashi, Fuminori},
  year = {2014}
}

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