article · Specialized and Legacy Electronics Manufacturing Conferences · 1998

Manufacturing Methodologies for High Density Interconnect Structures (HDIS)

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Abstract

ABSTRACT Supported by strong consumer demand for portability, without compromise to power, accessibility, features or weight, the electronics industry is entering into a new era. This new era is being witnessed at all levels of interconnect technology including, silicon wafer fabrication, PWB manufacturing, shielding for housings, and the cooling methods employed on large chips. In addressing these new requirements, a synergy of manufacturing methodologies is emerging. In silicon chip manufacturing, requirements for metallization of advanced semiconductor interconnections have resulted in a movement towards electroplated metal techniques long known to the PWB manufacturer. In PWB manufacturing, the requirement for finer lines and better utilization of PWB real-estate has given rise to micro via techniques. In concept, the sequential build up (SBU) used on the PWB has a fabrication flow which is not unlike wafer fabrication, where layers of circuitry are added over dielectrics and interlayer connections are made by selective removal of that dielectric from the connection points. For both industries, there is a tremendous learning curve to become efficient with these new manufacturing methods. Even the traditional roles of these two dominant component arms in electronic system evolution are converging. This is most notable in PWB manufacturing. After many years of hearing that future packaging was likely to include laminate based products, the day has finally arrived where there is a significant demand for these small, dense “PWBs”. Traditional PWB laminates such as FR-4 and BT epoxy resins are being used at the platform for these chip scale packages designed with motherboard interfacing styles including PGA, BGA, LGA or SMT mezzanine style connectors. These products are growing in global demand. The market is currently dominated by Japanese producers. A logical domestic source for these laminate based products is the PWB manufacturer. To compete with our Japanese counterparts, new technology will be required. This paper will discuss some manufacturing methods which can be used to produce High Density Interconnection Structures (HDIS) such as the laminate chip carriers and complex PWBs.

Cite this paper

APA 7

Nargi-Toth, K., & Gandhi, P. (1998). Manufacturing Methodologies for High Density Interconnect Structures (HDIS). Specialized and Legacy Electronics Manufacturing Conferences, 2(1). https://doi.org/10.37665/leuxcwp36579

MLA 9

Nargi-Toth, Kathleen, and Pradeep Gandhi. “Manufacturing Methodologies for High Density Interconnect Structures (HDIS).” Specialized and Legacy Electronics Manufacturing Conferences, vol. 2, no. 1, 1998, https://doi.org/10.37665/leuxcwp36579.

Chicago

Nargi-Toth, Kathleen, and Pradeep Gandhi. 1998. “Manufacturing Methodologies for High Density Interconnect Structures (HDIS).” Specialized and Legacy Electronics Manufacturing Conferences 2 (1). https://doi.org/10.37665/leuxcwp36579.

Harvard

Nargi-Toth, K. and Gandhi, P. (1998) ‘Manufacturing Methodologies for High Density Interconnect Structures (HDIS)’, Specialized and Legacy Electronics Manufacturing Conferences, 2(1). Available at: https://doi.org/10.37665/leuxcwp36579.

BibTeX

@article{nargitoth1998manufacturing,
  title = {{Manufacturing Methodologies for High Density Interconnect Structures (HDIS)}},
  author = {Nargi-Toth, Kathleen and Gandhi, Pradeep},
  journal = {Specialized and Legacy Electronics Manufacturing Conferences},
  volume = {2},
  number = {1},
  year = {1998},
  doi = {10.37665/leuxcwp36579}
}

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