article · Chips · 2026

Highly Parallel Sorting Network Verification Using FPGAs

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Abstract

Sorting networks are of prime importance as circuits, with applications in sorting small data chunks, big data analytics, permuting packets, and system interconnects. Finding optimal sorting networks is a highly complex problem, and knowledge on optimal sorting networks is limited. When optimising the network depth or the number of comparators, one of the most expensive tasks is considered to be verification, that is, to verify that the candidate compare-and-swap network actually sorts the data. This grows exponentially with the size of the sorting network. However, FPGAs allow vast amounts of internal parallelism, and our presented work exploits this flexibility using dataflow techniques to achieve unparalleled amounts of speedup for sorting network verification. This work can be used in a modular way to accelerate the search for optimal sorting networks with a high number of inputs, as well for similar verification problems.

Cite this paper

APA 7

Papaphilippou, P. (2026). Highly Parallel Sorting Network Verification Using FPGAs. Chips, 5(1), 5. https://doi.org/10.3390/chips5010005

MLA 9

Papaphilippou, Philippos. “Highly Parallel Sorting Network Verification Using FPGAs.” Chips, vol. 5, no. 1, 2026, p. 5, https://doi.org/10.3390/chips5010005.

Chicago

Papaphilippou, Philippos. 2026. “Highly Parallel Sorting Network Verification Using FPGAs.” Chips 5 (1): 5. https://doi.org/10.3390/chips5010005.

Harvard

Papaphilippou, P. (2026) ‘Highly Parallel Sorting Network Verification Using FPGAs’, Chips, 5(1), p. 5. Available at: https://doi.org/10.3390/chips5010005.

BibTeX

@article{papaphilippou2026highly,
  title = {{Highly Parallel Sorting Network Verification Using FPGAs}},
  author = {Papaphilippou, Philippos},
  journal = {Chips},
  volume = {5},
  number = {1},
  pages = {5},
  year = {2026},
  doi = {10.3390/chips5010005}
}

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