Parallelism extraction and program restructuring for parallel simulation of digital systems

Abstract

Two topics currently of interest to the computer aided design (CAD) for the very large scale integrated circuit (VLSI) community are using the VHSIC Hardware Description Language (VHDL) effectively and decreasing simulation times of VLSI designs through parallel execution of the simulator. The goal of our research is to increase the degree of parallelism obtainable in VHDL simulation, and consequently to decrease simulation times. Our research targets simulation on massively parallel architectures. Experimentation and instrumentation were done on the SIMD Connection Machine. In this thesis we discuss our method used to extract parallelism and restructure a VHDL program, experimental results using this method, and requirements for a parallel architecture for fast simulation.

Cite this paper

@article{vellandi1991parallelism,
  title = {{Parallelism extraction and program restructuring for parallel simulation of digital systems}},
  author = {Vellandi, Beverly Lynn},
  year = {1991}
}

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