Ken Bryan F. Fabay, John Cris F. Jardin, Kervin John C. . Jocson et al. · 2012
This paper presents an FPGA implementation of a test port for interfacing and debugging ARM9 processors. The system included a communication interface for debugging the processor, together with the JTAG-based module that granted debugging capability to the selected ARM9 core. Also included was an application software debugger that readily shows the comparison of expected and gathered results from the processor core. The debugging system for the selected ARM9 processor was successfully implemented in a Virtex 5 FPGA development board and was tested using the supported data processing instructions. The latency measured was 0.3 ms per instruction for a baud rate of 4800.
Cited by 2
Cui Guang · 2001
Based on hardware/software codesign, a new kind of system level simulation, emulation and debugging method(called SSED) is proposed, which can be conveniently used in processor design. This method can be described as follows: set up execution environment according to real world applications;translate C program into assembly program, execution code and input vector which is used in simulation and emulation; debug VHDL program with assembler program under a kind of time model; analyze the execution results. The design and implementation of Jbcore16 processor indicates that SSED can increase verification efficience and accelerate processor design and implementation speed.
Cited by 0
Yihong Zhang, Wei Tang · 2023
Aiming at the high reliability debugging needs of the system-on-chip of a RISC- V processor in the embedded field, a hardware debugging system based on the RISC- V debugging protocol is designed and implemented. The system uses JTAG signals to communicate with the debug host, and takes over the processor core control through the debug module, which not only realizes the basic debugging function, but also realizes the program cache execution function and hardware trigger function. In order to reduce the occupation of the pin interface, a two-wire debugging interface is designed. At the same time, the structure of the instruction transmission is optimized, and the instruction bypass transmission function is added to improve the reliability of the debugging system. The hardware debugging system has been verified by software simulation and FPGA prototype, and compared with the debugging systems of other RISC- V processors, and the results show that the hardware debugging system is feature-rich and can meet the functional requirements of debugging.
Cited by 1
Todd Allen, David Padua · University of North Texas Digital Library (University of North Texas) · 1987
Debugging on a parallel processor is more difficult than debugging on a serial machine because errors in a parallel program may introduce nondeterminism. The approach to parallel debugging presented here attempts to reduce the problem of debugging on a parallel machine to that of debugging on a serial machine by automatically detecting nondeterminism. 20 refs., 6 figs.
Cited by 48Open access
R. E. McLear, D. M. Scheibelhut, E. Tammaru · ACM SIGARCH Computer Architecture News · 1982
Hardware without software is of little use. Systems that ease the task of debugging software reduce cost and speed development. This paper presents guidelines for designing processors that ease debugging for real-time computer systems. Special hardware can aid the debugging process by tracing execution and accesses to memory. Such hardware requires access to signals that may not be readily available. Other, less exotic hardware provides an interface to the programmer and other processors. The hardware and software of the debugging system should not alter the real-time characteristics of the system under test and should be able to operate on a field-grade processor. It is undesirable to require special versions of processor hardware and software for the debugging system.
Cited by 2Open access
George S. Powley, Joanne DeGroat · 1994
We describe design decisions made while testing and debugging our behavioral VHDL model of the Intel i960 MX processor. The model provides human readable representations of processor information, to simplify debugging and documentation. An interactive simulation, using an X window interface, aids in debugging the VHDL model and application software. We developed an automated result checking entity to verify instruction operation tests and a flexible method to generate Chebyshev approximations of transcendental functions and check their results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 6
Guerriero, Lorenza · AMS Degree Thesis (University of Bologna)
This thesis addresses the need for a functional debug module for the 'nanorv' processor, a compact implementation of the open-source RISC-V instruction set. The growing adoption of RISC-V across academia and industry highlights the critical role of robust debugging infrastructure in embedded system development, especially for minimalist architectures where traditional debugging methods may not apply. The primary objective of this work is to design, implement, and validate a debug module for the nanorv processor. The module will comply with the RISC-V Debug Specification and be compatible with standard debugging tools via the JTAG interface. Essential functionalities, such as halting, resuming, and single-stepping the processor, will be supported. The methodology involves several key steps: analyzing the specific debug requirements of a simple processor like nanorv, designing a dedicated hardware-based module to interact with the processor's internal state, implementing communication interfaces with both the processor core and external tools, and finally, validating the entire system through simulations and practical testing. The successful outcome of this thesis will not only provide a much-needed, non-intrusive debug solution for the nanorv processor but will also offer a reusable blueprint for future applications involving similar lightweight processors.
Cited by 0
Dale Parson, Bryan Schlieder, Paul Beatty et al. · 2008
Embedded systems contain several layers of target processing abstraction. These layers include electronic circuit, binary machine code, mnemonic assembly code, and high-level procedural and object-oriented abstractions. Physical and temporal constraints and artifacts within physically embedded systems make it impossible for software engineers to operate at a single layer of processor abstraction. The Luxdbg embedded system debugger exposes these layers to debugger users, and it adds an additional layer, the extension language layer, that allows users to extend both the debugger and its target processor capabilities. Tcl is Luxdbg’s extension language. Luxdbg users can apply Tcl to automate interactive debugging steps, to redirect and to interconnect target processor input-output facilities, to schedule multiple processor execution, to log and to react to target processing exceptions, to automate target system testing, and to prototype new debugging features. Inclusion of an extension language like Tcl in a debugger promises additional advantages for distributed debugging, where debuggers can pass extension language expressions across computer networks. 2 1.
Cited by 0
Rajalakshmy Sivaramakrishnan, VR Sarasamma · Institutional Repository @ NAL (University of Southampton) · 1992
Flosolver Mk3 [1-2] consists of five single board computers based on the Intel 1860 RISC processor. One of the processor is the host and has the UNIX operating system. Other processing elements (PE) have only system debug monitor (iSDM) which permits limited access to disc. The debug monitor is used for the initial set up of PE's and debugging during program execution. The design given in this report shares a single display terminal among PE's for initial set up debugging.
Cited by 0
Zhang Meijuan, Xin Kunpeng, Wang Lijuan et al. · SHILAP Revista de lepidopterología · 2023
A debugging system based on JTAG interface is proposed in this paper to provide an effective and convenient debugging method for domestic processor chip. The debugging system, which is based on JTAG standard, simplifies the design of the on-chip debugging hardware module. With little hardware overhead, simple and high performance design of the debugging instruction, it is used to realize the debugging interrupt, breakpoint and watch point setting，single step running，register or memory read and write, and other base debugging functions, as well as sence protection and recovery, trace buffer, instruction insert execution and other advanced debugging functions. After passed the actual chip testing, the debugging system has compatibility with JTAG protocol, comprehensive functions, high performance, simple structure, convenient for operation and other features.
Cited by 0Open access
L.J. Moore, Alejos Moya · 2005
Trace debugging is a software diagnostic technique for embedded real-time systems. It is developed to give embedded software developers the ability to trace the activity of the processor even when it is operating out of cache. This ability is lost on many high performance processors and in real-time systems. Tools for debugging real-time systems are scarce (Lee, E., 2000; Zhang, L. and Yuan, P., 1999). This paper describes work that was performed on a new method of trace debugging that can be used to aid in real-time debugging of embedded software. The technique described uses non-intrusive measurements that are supplemented with deductive algorithms. The technique developed in the study differs from traditional debuggers by utilizing the a-priori information that is available. The study utilized a Motorola 68020 as a model of a high performance processor, but the processes are applicable to many "high performance" processors.
Cited by 15
Kui Wang · Trepo - Institutional Repository of Tampere University · 2013
This thesis introduces a debugging utility named Mobile Crash on Symbian OS. Mobile Crash is able to trap Symbian OS program panics and processor exceptions. It further collects program data and processor state that may help to solve the trapped failure, and sends the collected data for analysis. The thesis presents the background knowledge of embedded system development and Symbian OS to help the reader to understand the main topic. The thesis also discusses other ways to do debugging on Symbian OS, which include using emulator and tracing application execution. In addition, the thesis compares different debugging methods and gives general guidelines for applying these methods on Symbian OS development.\n\nKeywords:\n\nSymbian OS, Embedded System, Debug, Mobile Crash
Cited by 3Open access
Alejandro Caro, Campbell L. Searle · 1993
Debugging a program on a MIMD parallel processor is difficult due to the large amount of program state, the distribution of this state over many processors, and the dynamic interactions between processors which lead to unpredictable program behavior. The Monsoon parallel processor and its programming language Id add non-deterministic scheduling of instructions, implicit parallelism, non-strict semantics, and a polymorphic type system to an already complex problem. We introduce a novel data driven approach to debugging Id programs. In this model, the execution of a program produces a stream of debugging events that are interpreted by the debugger. The events provide a precise view of the flow of data through the program. By allowing the programmer to concentrate on data-flow rather than on control-flow, we provide a debugging environment well suited for Id. We describe the modifications made to the Id compiler in order to implement the mechanisms needed by our data driven debugger. We a...
Cited by 0
Branislav Vujović · 2010
In this thesis, a proposal was given to improve the existing architecture of a dynamic variable processor optimized for fast execution of various algorithms over large data sets. Analyzed behavior of the initial architecture has resulted with appropriate changes. Thesis gives description of the capabilities of individual components and their behavior during program execution. Suggested modeling and simulation techniques ensure various reconfigurable processor architectures. The proposed procedure allows changes to the architecture and extension of the simulator with other tools such as support for debugging. Development environment combines a text editor, assembler compiler and support for debugging.
Cited by 0
Ping Zhang, Zuocheng Xing · IEEE Conference Anthology · 2013
With the development of semiconductor technology and the complexity of chip, in some circumstance, the cost of repeated design and manufacture to modify the design mistakes is almost as large as initial design. The cache is an essential part of the processor, in order to ensure the correctness of the design and reduce the cost of debugging cache, the cache should be considered for design-for-debugging. In this paper, the debugging structure is specially designed for the debugging cache, and implemented in Z-CPU. It is convenient to debug the cache by the debugging structure which is simple in logic design, and is smaller in cost of hardware and is applicable to all general-purpose CPU chips.
Cited by 0
Greg Utas · 2004
This chapter contains sections titled: Language Object Management Tasks Critical Regions Scheduling I/O Messaging Fault Containment Error Recovery Overload Processor Failures Operability Software Installation Debugging Summary
Cited by 0
Habib ul Hasan Khan, Diana Göhringer · 2018
This research work presents an intrusive methodology for debugging of embedded designs by using artificial intelligence technique. In this methodology, a cycle-accurate lossless debugging system with unlimited trace window can be used for debugging. Visibility of the embedded hardware is enhanced by an access network which also eliminates the need for frequent re-synthesis due to change in signal set. The controlling processor can configure the required network through software. A connectivity tool is developed which permits error-free connection of the DUT with the debugging system by using IP-XACT files. A correspondence analysis between the debugging results of the implemented hardware and its simulation results can be performed to speed up the debugging process. The debugging system can be partially reconfigured to any embedded design at runtime which can not only reduce the time spent on iterative place and route process of traditional debugging solutions but also makes the FPGA resources available to the user when debugging is not required
Cited by 0
Jeffrey S. Brown · University of North Texas Digital Library (University of North Texas) · 1993
This report contains papers or viewgraphs on the following topics: The ABCs of Debugging in the 1990s; Cray Computer Corporation; Thinking Machines Corporation; Cray Research, Incorporated; Sun Microsystems, Inc; Kendall Square Research; The Effects of Register Allocation and Instruction Scheduling on Symbolic Debugging; Debugging Optimized Code: Currency Determination with Data Flow; A Debugging Tool for Parallel and Distributed Programs; Analyzing Traces of Parallel Programs Containing Semaphore Synchronization; Compile-time Support for Efficient Data Race Detection in Shared-Memory Parallel Programs; Direct Manipulation Techniques for Parallel Debuggers; Transparent Observation of XENOOPS Objects; A Parallel Software Monitor for Debugging and Performance Tools on Distributed Memory Multicomputers; Profiling Performance of Inter-Processor Communications in an iWarp Torus; The Application of Code Instrumentation Technology in the Los Alamos Debugger; and CXdb: The Road to Remote Debugging.
Cited by 1Open access
Jeff Gilles, Ray Ford · 2003
Embedded real-time control systems typically require the use of special debugging environments, which consist of a special debugging processor that hosts the debugging software and that monitors the execution of the separate target system via a special hardware interface. The focus is on extending the set of base debugging features typically found in such an environment to provide better support for real-time task debugging and a more visual graphic display of program behavior. A system was developed that provides such facilities, in the form of a task condition specification and checking system and multiwindow graphics display. A prototype of these novel debugging features was implemented which demonstrates how they work and how they assist in the debugging process. The features of the system are illustrated by providing a tour through an example debugging session. Various constraints that directed the prototype development process are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 5
2005
The following topics are dealt with: processor architecture; computer temperature, energy and power; communication architectures; energy and power reduction; memory system; industrial perspectives; evaluation methodologies; software debugging support; multiprocessors and multithreading.
Cited by 216